Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1994-10-31
1996-10-29
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257690, 257693, 257700, 257731, H01L 2352, H01L 2348, H01L 23053, H01L 2312
Patent
active
055699570
ABSTRACT:
Lead inductance of a power MOSFET circuit layouts is effectively reduced a `vertically` parallel terminal lead configuration that serves to cancel magnetic flux linkage between adjacent leads, thereby reducing the effective inductance in terminal leads to the gate, source and drain regions of the circuit. Rather than lay out source, drain and gate terminal leads in long, meandering shapes without regard to their direction or mutual coupling effects, as in conventional structures, source and drain leads are arranged as vertically parallel pair of generally flat conductors, that overlie one another on opposite sides of a thin strip of insulating material. Because of the substantially identical vertical geometry projection of these generally flat conductors upon one another on opposite sides of a thin strip of insulating material, forward and return current through the flat conductors are caused to be in close proximity with each other, thereby effecting magnetic flux linkage cancellation and significantly reducing the effective inductance of the source and drain conductors. Similarly, gate conductor and a source Kelvin leads of a like flat shape are disposed on opposite sides of another thin insulating stripe, which is mounted at a location of a support substrate spaced apart from the mounting location of the source--drain laminate structure. Direct wire bonding may be employed to electrically connect the flat conductors to the MOSFET device.
REFERENCES:
patent: 5038197 (1991-08-01), Satriano
patent: 5424579 (1995-06-01), Arai et al.
Harris Corporation
Loke Steven H.
Wands Charles E.
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