Electric power conversion systems – Current conversion – Integrated circuit
Reexamination Certificate
2001-07-31
2002-04-30
Riley, Shawn (Department: 2838)
Electric power conversion systems
Current conversion
Integrated circuit
Reexamination Certificate
active
06381161
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit arrangement or circuit configuration including high-performance rectifiers and low inductance. In particular the present invention relates to a circuit arrangement having high-performance rectifiers using semiconductor switches to minimize operation time, minimize power loss, and parasitic inductance.
2. Description of the Related Art
The prior art has recognized the desirability to reduce operation time and reduce power loss. It is known that circuit arrangements including MOSFETs (metallic oxide semiconductor field-effect transistors) or IGBTs (insulated gate bipolar transistors) with antiparallel-connected free-running diodes are well suited to operate relatively quickly and with reduced power loss.
The circuit arrangements include rectifiers and must be of low-inductance design to prevent the generation of voltage spikes. The voltage spikes especially occur during power-off operation. This means that to minimize voltage spikes, circuit arrangements must have low leakage inductances in an intermediate circuit, on connecting leads, and on the substrate surface itself. In the case of low-voltage MOSFETs, even leakage inductances in the 20 nH (nanohenry) range may lead to voltage spikes which can destroy the semiconductor switches.
There are many prior art examples including individual and semiconductor modules with individual design features specifically directed to reduce parasitic inductance. Examples of these are EP 0277 546, DE 39 37 045, and EP 0 609 528.
EP 0 277 546 describes a method of reducing parasitic inductances in the direct-current leads of individual switches. In this reference, two DC leads are arranged in close proximity and are at least partly parallel to each other. This arrangement causes a small current-diffuse area in a region of closely adjacent leads, and this sector of the leads is therefore of low inductance.
DE 39 37 045 describes a method for reducing parasitic inductances in the DC leads of a half-bridge. In this reference, two DC leads are in close proximity, but with an AC lead between the positive and negative lines. The leads are at least partly parallel to each other. This causes a reduction in size of the current-circumfused area in the region of the closely adjacent lead configuration and thus a relatively low inductance of this lead sector.
EP 0 609 528 also describes a method for reducing parasitic inductances in a parallel and closely adjacent DC leads of an individual switch. In this reference, the semiconductor components are arranged symmetrically on a substrate.
The prior art also includes power semiconductor modules in pressure contact technology. Examples of this technology can be found in DE 196 30 173 and DE 593 06 387. This type of power semiconductor module consists of ceramic substrates to which contact surfaces are applied, and on which semiconductor components are arranged.
The semiconductor components are connected to contact surfaces by soldering. The semiconductor components have bond connections to other semiconductor components or other second contact surfaces which are applied to the substrate and insulated against the first contact surface.
In this type of construction, pressure contacting relates to two different types of bonds. A first type of bond is the electrical bond of the leads with the associated contact surfaces of the substrate. The second type of bond is a thermal bond between the substrates or between the entire module and a cooling body. In these types of bonds, plastic elements can be used, which transfer pressure applied to the module from the outside, to the connecting elements and/or to the substrate to establish a secure electrical or thermal contact.
All low-inductance circuit arrangements described in prior art have in common that they achieve a certain reduction of parasitic inductances only in the partial areas of the overall system of intermediate circuit-rectifier. The best values that can thus be achieved for the overall inductance of this system are presently above 20 nH (nanohenry).
In EP 0 277 546, the transistors forming the individual switch are in close proximity to each other, and yet the current can flow through the circuit arrangement along different paths, and in particular, along paths of different lengths. This current flow causes different current-circumfused areas and also different inductances for the different conduction paths. Current-circumfused means that the current flows around a certain area. In drawings referring to a current-circumfused area, the current-circumfused area may be represented as a shaded section.
Unfortunately, the design of a half-bridge with this type of individual switches can never be low-inductance because of the necessary external circuitry. Taking all characteristics together, these designs may lead to a certain reduction in the parasitic inductances of the overall system intermediate circuit/DC/AC converter. However, this reduction still does not meet all the consumer and design requirements of minimizing parasitic inductances.
Particularly, DE 39 37 045 fails to meet the goal of minimizing parasitic inductance for two major reasons. The first reason is that the DC leads are not arranged at a minimal distance from each other, since the AC lead is arranged between the two DC leads. Thus the current-circumfused area in the region of the DC leads is not minimal, and the inductances for this region are correspondingly not minimal. The second reason is that the power transistors of the first and second power switches are arranged relatively far distant from each other, which also increases the parasitic inductances.
Referring now to
FIG. 1
, showing a typical design of a half-bridge intermediate circuit. The intermediate circuit includes a capacitor
1
with at least one positive lead
2
, at least one negative lead
3
, and at least one power switch
4
.
Power switches
4
may be designed as MOSFETs or IGBTs. If power switches
4
are designed as IGBTs, an additional free-running diode
5
is required on each power switch
4
. An AC lead
6
is supplied between power switches
4
. A current flow
7
occurs from positive lead
2
to negative lead
3
during a commutation process. Current flow
7
flows around a current-circumfused area
8
. The size of current-circumfused area
8
is a direct measure for the parasitic inductances which occur and illustrates the cross section of a coil with one winding.
Additionally referring now to
FIG. 2
showing a realistic case of circuit arrangement similar to
FIG. 1
where first and second power switches
4
include several parallel-connected power transistors. As a result of the additional power transistors, current flow
7
and current-circumfused area
8
are different. This design emphasizes that since the shape of current-circumfused area
8
changes relative to the additional transistors, the associated inductances for each power transistor are different.
Additionally referring now
FIG. 3
, a ceramic substrate
9
supports a positive lead
17
having as a positive surface a copper laminated surface
12
. Ceramic substrate
9
also supports a negative lead
16
with a copper laminated surface
10
and an AC lead
18
with a copper laminated surface
11
. For simplicity, auxiliary connections such as a gate, a base, or auxiliary emitters, are not shown.
On the plus area are multiple first power transistors
13
which constitute a first power switch, and a free-running diode
14
. Bond wires
15
connect emitters of the power transistors to surface
11
of AC lead
18
.
Arranged on surface
11
of AC lead
18
are second power transistors
19
as well as a second free-running diode. Bond wires
15
connect second power transistors
19
to the copper laminated surface
10
of negative lead
16
.
Positive lead
17
, negative lead
16
and AC lead
18
are also arranged on each respective surface matching their polarity. Typical for such arrangements, according to prior art, is an arrangement where positive and n
Morrison Law Firm
Riley Shawn
Semikron Elektronik GmbH
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