Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2000-03-07
2001-08-21
Reichard, Dean A. (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S301500, C361S517000, C361S535000
Reexamination Certificate
active
06278603
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The invention is related to the field of capacitors used in uninterruptible power supplies and similar power systems.
Large capacitors are used in power supplies to provide desired filtering and hold-up of DC bus voltages under transient conditions. It is common to employ a “bank” of several such capacitors connected in parallel in order to achieve a large aggregate capacitance value. The parallel connections among the capacitors are often achieved using conductive “buses” having large current-carrying capacities. For example, two closely-spaced buses may run along a capacitor bank, one bus carrying a ground connection, for example, and the other carrying an output DC voltage connection, such as for example 800 volts DC. The parallel connection is achieved by connecting one bus to one terminal of each capacitor, and the other bus to the other terminal of each capacitor. In one common arrangement the buses are separate layers of a multi-layer planar bus structure.
When multiple cylindrical capacitors are used in a capacitor bank, it is desirable that they be placed in an upright position with respect to the bus structure in order to maximize packaging density, i.e., to realize the greatest amount of capacitance in a given space. However, the capacitors typically have their two terminals located at different ends of the capacitor body. The upper capacitor terminal must be connected to the respective bus in the multi-layer structure located at the other end of the capacitor. In prior systems, this connection has been made using a low-gauge wire running alongside the capacitor body from the upper terminal to the respective bus. Unfortunately, such a wire introduces additional inductance in the electrical path between the capacitor and the buses, increasing the amplitude of voltage spikes experienced by switching devices connected to the buses. It would be desirable to significantly reduce such inductance without sacrificing the spatial density achieved with the upright mounting of capacitors in a capacitor bank.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a capacitor and capacitor mounting arrangement are disclosed in which the inductance of the connection between a connection bus and an upper terminal of an upright capacitor is significantly reduced from prior approaches. The packaging density associated with upright capacitor mounting is retained, while the stray inductance in the capacitor connections is reduced.
The disclosed capacitor includes a capacitor body containing the capacitive conductive plates. The capacitor body has a first end and a second opposing end. A conductive shell is disposed around the capacitor body. The conductive shell has a first end conductively connected to a first one of the conductive plates at the first end of the capacitor body. The conductive shell also has flexible conductive members disposed at a second end of the shell adjacent to the second end of the capacitor body. The flexible conductive members extend away from the capacitor body so as to be brought into conductive contact with a conductive surface against which the capacitor is to be mounted in use, such as an upper layer of a multi-layer bus.
Because of the large surface area of the conductive shell and the manner in which the shell contacts the conductive surface, the inductance between the conductive surface and the first plate of the capacitor and the second plate of the capacitor can be substantially less than in prior capacitor mounting arrangements. When the capacitor is used to filter the output of a power supply, this reduced inductance results in reducing the amplitude of voltage spikes experienced by switching devices connected to the output.
Other aspects, features, and advantages of the present invention are disclosed in the detailed description that follows.
REFERENCES:
patent: 1830907 (1931-11-01), Kindl
patent: 3024393 (1962-03-01), Ferrante
patent: 5493471 (1996-02-01), Walther et al.
Arbanas Zelijko
Galante Richard J.
Acumentrics Corporation
Reichard Dean A.
Thomas Eric
Weingarten, Schurgin Gagnebin & Hayes LLP
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