Low impedance column multiplexer circuit and method

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S205000, C327S589000

Reexamination Certificate

active

07821866

ABSTRACT:
The invention has a bootstrapped high voltage pass gate transistor that couples the low voltage sense amplifier to the bitlines. Since the pass gate transistor is bootstrapped its gate floats to the high voltage of the power supply (VCC) plus a delta voltage. This overdrives the pass gate transistor and allows it to pass signals between the sense amplifier and the bitlines with low impedance. This results in good sense differential margins and fast read speeds. The circuit has a pass gate control circuit that places a negative high voltage signal on the gate of the pass gate during non-volatile write operations. This causes the pass gate to isolate the low voltage circuit from the high voltage circuits during this operation. Finally, the circuit is smaller than earlier column multiplexer circuits.

REFERENCES:
patent: 4433257 (1984-02-01), Kinoshita
patent: 4644189 (1987-02-01), Gabillard
patent: 4737670 (1988-04-01), Chan
patent: 4803665 (1989-02-01), Kasa
patent: 4807191 (1989-02-01), Flannagan
patent: 4849937 (1989-07-01), Yoshimoto
patent: 5059825 (1991-10-01), Yoshida
patent: 5062082 (1991-10-01), Choi
patent: 5083294 (1992-01-01), Okajima
patent: 5157283 (1992-10-01), Kin
patent: 5214606 (1993-05-01), Hashimoto
patent: 5216290 (1993-06-01), Childers
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5267205 (1993-11-01), Hamada
patent: 5357479 (1994-10-01), Matsui
patent: 5376829 (1994-12-01), Rogers et al.
patent: 5391941 (1995-02-01), Landry
patent: 5493241 (1996-02-01), Landry et al.
patent: 5598114 (1997-01-01), Jamshidi
patent: 5701095 (1997-12-01), Ohsawa
patent: 5731725 (1998-03-01), Rothenberger et al.
patent: 5844840 (1998-12-01), Le et al.
patent: 5982220 (1999-11-01), Kim
patent: 6078513 (2000-06-01), Ong et al.
patent: 6137340 (2000-10-01), Goodell et al.
patent: 6194950 (2001-02-01), Kibar et al.
patent: 6211722 (2001-04-01), Mattia et al.
patent: 6239646 (2001-05-01), Navabi et al.
patent: 6404237 (2002-06-01), Mathew et al.
patent: 6486712 (2002-11-01), Landry et al.
patent: 6501324 (2002-12-01), Ruegg et al.
patent: 6563367 (2003-05-01), Lee
patent: 6636077 (2003-10-01), Chang et al.
patent: 6650167 (2003-11-01), Benzer et al.
patent: 6696880 (2004-02-01), Pan et al.
patent: 6819141 (2004-11-01), Qi et al.
patent: 6853233 (2005-02-01), Terletzki et al.
patent: 6859391 (2005-02-01), Combe et al.
patent: 6879191 (2005-04-01), Davis
patent: 6956411 (2005-10-01), Holloway
patent: 6970116 (2005-11-01), Masaki
patent: 7030684 (2006-04-01), Kim
patent: 7099200 (2006-08-01), Sakui
patent: 7471135 (2008-12-01), Raghavan et al.
patent: 0314034 (1988-10-01), None
USPTO Notice of Allowance for U.S. Appl. No. 11/566,767 dated Sep. 11, 2008; 3 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/566,767 dated Aug. 15, 2008; 6 pages.
USPTO Non Final Rejection for U.S. Appl. No. 11/566,767 dated Mar. 11, 2008; 6 pages.
International Search Report and Written Opinion of the International Searching Authority for International Application No. PCT/US2007/085838 mailed Jun. 18, 2008; 11 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/182,556 dated Jan. 26, 2001; 3 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/182,556 dated Sep. 8, 2000; 7 pages.
USPTO Final Rejection for U.S. Appl. No. 09/182,556 dated May 23, 2000; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/182,556 dated Jan. 6, 2000; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/740,106 dated Jul. 1, 2002; 3 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/740,106 dated Feb. 27 2000; 6 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/340,252 dated Aug. 8, 1995; 1 page.
USPTO Non-Final Rejection for U.S. Appl. No. 08/340,252 dated Apr. 20, 1995; 3 pages.
Fitzgerald el al., “Memory System with High-Performance Word Redundancy,” IMB Technical Disclosure Bulletin, Oct. 1976, vol. 19, No. 5, pp. 1638-1639; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/126,069 dated Jul. 27, 1994; 5 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Low impedance column multiplexer circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low impedance column multiplexer circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low impedance column multiplexer circuit and method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4163682

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.