Low hold time statisized dynamic flip-flop

Details Low hold time statisized dynamic flip-flop Low hold time statisized dynamic flip-flop

2001-06-07

2002-09-10

Cunnigham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000, C327S211000, C327S213000

Reexamination Certificate

active

06448829

ABSTRACT:

BACKGROUND OF INVENTION
The design of a computer system may be broken down into three parts—system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form logic building blocks.
One such logic building block is a flip-flop. A flip-flop is a memory element that that provides storage for at least one bit, i.e., it can at least store a ‘1’ or a ‘0.’ A type of flip-flop commonly used by high performance circuits is a static flip-flop (discussed below with reference to FIG.
1
).
An important aspect of circuit design is how logic building blocks, such as flip-flops, are actually implemented in a computer system. A typical approach used to implement logic building blocks is through the use of complementary metal-oxide-semiconductor (“CMOS”) logic families. CMOS logic families use metal-oxide-semiconductor field-effect transistors (“MOSFETs”).
The use of MOSFET transistors is beneficial because lower currents are needed to operate these transistors than other types of devices. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (“PMOS”) transistors and negative-channel metal-oxide semiconductor (“NMOS”) transistors. A transistor is ‘on’ when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched ‘on’ or ‘off’ by the movement of electrons, whereas PMOS transistors can be switched ‘on’ or ‘off’ by the movement of electron vacancies. Every MOSFET has a voltage threshold (“V
T
”) value, which is the voltage level at which the MOSFET switches ‘on’ or ‘off.’ Generally, an NMOS transistor switches ‘on’ when there is a high logic level applied to the input of the NMOS transistor and a PMOS transistor switches ‘on’ when there is a low logic level, e.g., ground, applied to the input of the PMOS transistor.
An implementation where the use of MOSFETs is exemplified involves a static flip-flop.
FIG. 1
shows a circuit schematic of a typical conventional static flip-flop (
10
). The static flip-flop (
10
) includes a master stage (
12
) that drives a slave stage (
14
). Such static flip-flops are also known as “master-slave static flip-flops.”
The master stage (
12
) includes a first transmission gate (
16
) that is formed by a first PMOS transistor (
18
) and a first NMOS transistor (
20
), where the first PMOS transistor (
18
) and the first NMOS transistor (
20
) are in parallel. A data input, DATA, serves as an input to the master stage (
12
), and, in turn, serves as an input to the first transmission gate (
16
).
The first transmission gate (
16
) outputs to a first inverter (
22
), which, in turn, outputs to both the slave stage (
14
) and a second inverter (
24
). The second inverter (
24
) outputs back to the input of the first inverter (
22
). The configuration of the first and second inverters (
22
,
24
) allows the value outputted to the slave stage (
14
) to be held constant when the first transmission gate (
16
) is switched ‘off,’ i.e., when data cannot pass through the first transmission gate (
16
).
The slave stage (
14
) includes a second transmission gate (
26
) formed by a second PMOS transistor (
28
) and a second NMOS transistor (
30
), where the second PMOS transistor (
28
) and the second NMOS transistor (
30
) are in parallel. The value outputted by the first inverter (
22
) in the master stage (
12
) serves as an input to the second transmission gate (
26
).
The second transmission gate (
26
) outputs to a third inverter (
32
), which, in turn, outputs to both an output, OUT, of the static flip-flop (
10
) and a fourth inverter (
34
). The fourth inverter (
34
) outputs back to the input of the third inverter (
32
). The configuration of the third and fourth inverters (
32
,
34
) allows the value outputted to OUT to be held constant when the second transmission gate (
26
) is switched ‘off,’ i.e., when data cannot pass through the second transmission gate (
26
).
A clock signal, CLK, serves as an input to the first PMOS transistor (
18
), and an inverted clock signal, INV_CLK, serves as an input to the first NMOS transistor (
20
). Alternatively, CLK serves as an input to the second NMOS transistor (
30
), and INV_CLK serves as an input to the second PMOS transistor (
28
).
When CLK is at a low logic level (also referred to also as being “low”) and INV_CLK is accordingly at a high logic level (also referred to as being “high”), the first transmission gate (
16
) switches ‘on,’ i.e., conducts, because the first PMOS transistor (
18
) switches ‘on’ due to the low value of CLK at its input and because the first NMOS transistor (
20
) switches ‘on’ due to the high value of INV_CLK at its input. Because the first transmission gate (
16
) is switched ‘on,’ the value of DATA is able to pass through the first transmission gate (
16
) to the input of the first inverter (
22
), which, in turn, outputs the inverse of DATA to both the slave stage (
14
) and the second inverter (
24
).
Conversely, because CLK is low and INV_CLK is high, the second transmission gate (
26
) is switched ‘off,’ and, as a result, the value outputted from the first inverter (
22
) is not able to pass through the second transmission gate (
26
). However, because the second inverter (
24
) inputs the value outputted by the first inverter (
22
) and subsequently outputs back to the input of the first inverter (
22
), the value outputted from the first inverter (
22
) is held constant at the input of the second transmission gate (
26
).
When CLK goes high and INV_CLK accordingly goes low, the second transmission gate (
26
) switches ‘on’ because the second PMOS transistor (
28
) switches ‘on’ due to the low value of INV_CLK at its input and because the second NMOS transistor (
30
) switches ‘on’ due to the high value of CLK at its input. Because the second transmission gate (
26
) is now switched ‘on,’ the value outputted by the master stage (
12
) is able to pass through the second transmission gate (
26
) to the input of the third inverter (
32
), which, in turn, outputs the inverse of the value outputted by the master stage (
12
) to both OUT and the fourth inverter (
34
). Furthermore, because the fourth inverter (
34
) inputs the value outputted by the third inverter (
32
) and subsequently outputs back to the input of the third inverter (
32
), the value outputted from the third inverter (
32
) is held constant at OUT regardless of whether the second transmission gate (
26
) switches back ‘off.’ However, when the master stage (
12
) again drives the slave stage (
14
), OUT will change accordingly, i.e., the third and fourth inverters (
32
,
34
) are strong enough to hold the value at OUT, but not strong enough to hold OUT when a value passes from the master stage (
12
) through the second transmission gate (
26
) to the input of the third inverter (
32
).
The static flip-flop (
10
) shown in
FIG. 1
may be modified for testing purposes to include scan test capabilities.
FIG. 2
shows a scan capable flip-flop (
40
) which can conduct both normal mode operations and scan mode operations. Normal mode operations include those operations dependent on actual input data, whereas scan mode operations include those operations dependent on a scan input value.
FIG. 2
includes a scan

Affiliated with

Also associated with

Rating

Low hold time statisized dynamic flip-flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low hold time statisized dynamic flip-flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low hold time statisized dynamic flip-flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2901044