Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-11-20
2004-03-16
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C326S027000, C326S082000, C326S083000
Reexamination Certificate
active
06707324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output driver, particularly to an output driver with low ground bounce.
2. Description of the Prior Art
A CMOS digital output driver is a well known circuit that outputs a logic high or a logic low to a load capacitance by charging or discharging the load capacitance. In practice, several output drivers are often connected to the same ground (GND) line and the same power supply (VCC) line.
One of the problems associated with connecting several noisy (high di/dt) output drivers to the same ground line is that significant ground bounce (switching noise) can be generated when many (or all) of these output drivers discharge their load capacitances at the same time.
FIG. 1
shows a circuit diagram that illustrates a basic output driver circuit. The driver circuit includes a p-channel transistor
11
and an n-channel transistor
12
.
The p-channel transistor
11
has a source connected to a power supply VCC, a drain connected to an output pad
13
, and a gate. The n-channel transistor
12
has a source connected to a ground, a drain connected to the drain of the p-channel transistor
11
, and a gate.
During normal operation, when the output driver is switched from a logic high to a logic low, a time varying current i
D
(t) from the pad
13
flows through the n-channel transistor
12
to the ground. The time varying current i
D
(t) causes the voltage on the source of the n-channel transistor
12
to increase due to an inductance
15
of pins or bondwires connected to the ground. As shown in the equation 1, the voltage variation VLG on on the source of the n-channel transistor
12
is defined as follows:
VLG=L*(dihd D (t)/dt) . . . (1)
where L represents the inductance
15
and di
D
(t)/dt represents the time varying discharge current i
D
(t).
Thus, as shown in the equation 1, extremely high ground bounce (switching noise) can be generated when several drivers are switched from a logic high to a logic low at the same time.
Similarly, a significant power supply bounce (switching noise) can be generated when several noisy (high di/dt) output drivers charge their load capacitances from the same power supply line at the same time.
Thus, in view of the above, there is a need for an output driver that can minimize the ground bounce and power supply bounce that can occur when several high di/dt output drivers discharge or charge their load capacitances at the same time.
Additionally, a crossbar current which is the short circuit current during the transition time when both the n-channel and p-channel transistors are partially on contributes to a high di/dt.
FIG. 2
shows a prior art output driver circuit with a re-driver. The pre-driver performs waveform shaping to reduce the crossbar current.
The output driver circuit operates on output signals from a pre-driver circuit
26
comprising a NOR gate, a NAND gate and an inverter. The pre-driver circuit
26
turns off the p-channel transistor
12
faster when the n-channel transistor
11
is turned on. Similarly, The pre-driver circuit
26
turns off the n-channel transistor
11
faster when the p-channel transistor
12
is turned on. This reduces the transition time when both the n-channel and p-channel transistors are partially on as well as the crossbar current.
FIG.3
is a diagram showing a prior art output driver circuit with RC delay circuits. The output driver circuit includes three parallel output drivers respectively composed of a p-channel transistor
31
a
and a n-channel transistor
32
a
, a p-channel transistor
31
b
and a n-channel transistor
32
b
, and a p-channel transistor
31
c
and a n-channel transistor
32
c
. Each of the transistors has an RC delay circuit connected to the gate. The RC delay circuits prevent the three output drivers being switched simultaneously. This minimizes the ground bounce and power supply bounce.
FIG.4
is a diagram showing another prior art output driver circuit comprising multiple output drivers. The output driver circuit shown in
FIG. 4
reduces the crossbar current and also prevents parallel output drivers being switched simultaneously.
SUMMARY OF THE INVENTION
The present invention provides an output driver with low ground bounce. The output driver receives a data signal and comprises a first transistor of a first type, having a drain connected to a pad, a source connected to receive a first power supply voltage and a gate, a capacitor with one end connected to receive the first power supply voltage and the other end connected to a charging/discharging node, a charging/discharging circuit generating a charging/discharging current output from the charging/discharging node when the data signal is at a first level, a first switch coupling the charging/discharging node to a second power supply voltage when the data signal is at a second level, and a second switch coupling the gate of the first transistor to the charging/discharging node when the data signal is at the first level and coupling the gate of the first transistor to receive the first power supply voltage when the data signal is at the second level.
The present invention further provides an output driver with low ground bounce receiving a data signal. The output driver comprises a first transistor of a first type, having a drain connected to a pad, a source connected to receive a first power supply voltage and a gate, a second transistor of a second type, having a drain connected to the pad, a source connected to receive a second power supply voltage and a gate, a first capacitor with one end connected to receive the first power supply voltage and the other end connected to a charging node, a second capacitor with one end connected to receive the second power supply voltage and the other end connected to a discharging node, a charging circuit generating a charging current output from the charging node when the data signal is at a first level, a discharging circuit generating a discharging current output from the discharging node when the data signal is at a second level, a first switch coupling the charging node to the second power supply voltage when the data signal is at the second level, a second switch coupling the discharging node to the first power supply voltage when the data signal is at the first level, a third switch coupling the gate of the first transistor to the charging node when the data signal is at the first level and coupling the gate of the first transistor to receive the first power supply voltage when the data signal is at the second level, and a fourth switch coupling the gate of the second transistor to the discharging node when the data signal is at the second level and coupling the gate of the second transistor to receive the second power supply voltage when the data signal is at the first level.
The present invention also provides an output driver for processing a data signal, comprising: a charging/discharging circuit for generating a charging/discharging current output signal on an output node when the voltage level of the data signal is at a first level, a first transistor of a first type, having a drain connected to a pad, a source connected to a ground voltage for receiving a first power supply voltage and a gate, a first switch coupling the output node of the charging/discharging circuit to a charging/discharging node when the voltage level of the data signal is at the first level, and coupling the output node to a second power supply voltage when the voltage level of the data signal is at a second level; and, a second switch coupling the gate of the first transistor to the output node when the data signal is at the first level and coupling the gate of the first transistor to receive the first power supply voltage when the data signal is at the second level.
REFERENCES:
patent: 4880997 (1989-11-01), Steele
patent: 5877638 (1999-03-01), Lin
patent: 6043702 (2000-03-01), Singh
patent: 6459325 (2002-10-01), Hall et al.
Lam Tuan T.
Rabin & Berdo P.C.
Via Technologies Inc.
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