Low gate resistance layout procedure for RF transistor devices

Details Low gate resistance layout procedure for RF transistor devices Low gate resistance layout procedure for RF transistor devices

2005-10-25

2005-10-25

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S757000, C257S377000

Reexamination Certificate

active

06958541

ABSTRACT:
A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.

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Weste, Neil et al.; Principles of CMOS VLSI Design; Addison-Wesley Pub. Co.; Oct., 1994; 113-116, 132-133.
Sze; VLSI Technology; McGraw-Hill; 1988; pp. 416-417.

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