Low frequency self-calibration of a PLL with multiphase clocks

Details Low frequency self-calibration of a PLL with multiphase clocks Low frequency self-calibration of a PLL with multiphase clocks

2007-11-20

2007-11-20

Kumar, Pankaj (Department: 2611)

Pulse or digital communications

Multilevel

Synchronized

Reexamination Certificate

active

10718256

ABSTRACT:
A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop is coupled to the Phase Frequency Detector, and comprises a Calibration Charge Pump, a Demultiplexer and Y Calibration Loop Filters, with Y being an integer. The Control Logic controls the Phase-Switching Fractional Divider and the Demultiplexer. A Reference Frequency Signal is coupled to the Phase Frequency Detector and a Calibration Signal is coupled to the calibration loop. The main loop further comprises a Phase-adjusting Block coupled to a Multiplexer. The Phase-adjusting Block is arranged so as to receive at least one correction signal from the calibration loop.

REFERENCES:
patent: 6064272 (2000-05-01), Rhee
patent: 6181213 (2001-01-01), Chang
patent: 1 133 060 (2001-09-01), None
Park, Chan-Hong, “A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching”, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 777-783, XP002241677.
European Search Report dated May 20, 2003 for European Application No. 02447228.4.

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