Low frequency detection circuit

Details Low frequency detection circuit Low frequency detection circuit

1999-05-14

2001-01-23

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By frequency

C327S043000

Reexamination Certificate

active

06177813

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a low frequency detection circuit, and more particularly, to an improved low frequency detection circuit, wherein a delay locked loop circuit for a semiconductor memory being operated at a high frequency can also be operated at a low frequency.
2. Description of the Background Art
The composition of a conventional sub-delay generation circuit will now be described with reference to the accompanying drawings.
FIG. 1
shows a negative delay signal generation circuit according to the conventional art. As shown therein, the circuit includes a pulse generator
10
for receiving an externally applied clock signal CK and generating a one shot pulse signal S
1
, a delay array
11
for receiving the one shot pulse signal S
1
and outputting a delayed one shot pulse signal S
2
, a forward delay array
12
for receiving the delayed one shot pulse signal S
2
and outputting a plurality of delay signals DS
1
-DS
6
, a mirror control circuit
13
for receiving the plurality of delay signals DS
1
-DS
6
and outputting a plurality of locking signals S
3
-S
8
in accordance with the one shot pulse signal S
1
, a backward delay array
14
for receiving the plurality of locking signals S
3
-S
8
and outputting sequentially delayed output signals DS
7
-DS
12
, a dummy delay array
15
for receiving the output signals DS
7
-DS
12
of the backward delay array
14
and decreasing power of the output signals DS
7
-DS
12
, and a delay array
16
for receiving and delaying the output signal DS
12
of the backward delay array
14
and outputting a negative delay signal CKO.
Here, the negative delay signal generation circuit will now be explained in further detail.
The pulse generator
10
includes an inverter
11
for inverting a clock signal CK, a NAND gate ND
1
for NANDing the clock signal CK and the output signal of the inverter I
1
, and an inverter I
2
for inverting an output signal of the NAND gate ND
1
and outputting a one shot pulse signal S
1
.
The delay array
11
includes inverters I
3
, I
4
and buffers B
1
, B
2
which are serially connected and for receiving and delaying the one shot pulse signal S
1
.
The forward delay array
12
includes a plurality of delay arrays D
1
-D
6
serially connected with each other and for receiving the delayed one shot pulse signal S
2
and respectively outputting the delayed one shot pulse signals DS
1
-DS
6
. Here, the delay array D
1
includes a NAND gate ND
2
for NANDing the delayed one shot pulse signal S
2
and the source voltage Vcc, and an inverter
15
for inverting the output signal of the NAND gate ND
2
. Also, the other delay arrays D
2
-D
6
are provided in the same as the delay array D
1
in composition.
The mirror control circuit
13
includes a plurality of NAND gates ND
3
-ND
8
for NANDing the output signals DS
1
-DS
6
of the forward delay circuit
12
and the one shot pulse signal Si.
The backward delay circuit
14
includes a plurality of delay arrays D
7
-D
12
for receiving a plurality of locking signals S
30
S
8
outputted from the mirror control circuit
13
and sequentially delaying the received values. Here, the delay array D
7
includes a NAND gate ND
9
for NANDing the input signal S
3
and the source voltage Vcc, and an inverter
16
for inverting the output signal of the NAND gate ND
9
. The other delay arrays D
8
-D
12
is also composed of the same as the delay array D
7
in circuit device composition.
The dummy delay array
15
is composed of a plurality of NAND gates ND
10
A-ND
10
F for respectively NANDing the plurality of locking signals DS
7
-DS
12
and the ground voltage Vss.
The delay array
16
includes inverters
17
,
18
serially connected to each other to delay the output signal DS
12
of the backward delay circuit
14
.
The operation of the conventional negative delay signal generation circuit will now be explained with reference to
FIGS. 2A through 2G
.
The pulse generator
10
which has received a clock signal CK as shown in
FIG. 2A
, generates the one shot pulse signal S
1
delayed by time period t
1
and having pulse width PW
1
, as shown in
FIG. 2B
, and outputs the generated value to the delay array
11
and the mirror control circuit
13
. The delay array
11
which has received the one shot pulse signal S
1
, as shown in
FIG. 2C
, delays the received value by time period t
2
and outputs the one shot pulse signal S
2
to the forward delay circuit
12
. The plurality of serially connected delay arrays D
1
-D
6
in the forward delay circuit
12
which receives the delayed one shot pulse signal S
2
respectively delay the delayed one shot pulse signal S
2
and accordingly output a plurality of output signals DS
1
-DS
6
. Then, the NAND gate ND
13
of the mirror control circuit
13
NANDs the signal DS
6
outputted from the delay array D
6
after being delayed by t
3
of the signal S
2
as show in
FIG. 2D
, and the one shot pulse signal S
1
after the time period t
2
+t
3
lapses further than the previous one shot pulse signal as shown in
FIG. 2B
, and then outputs the locked signal S
3
as shown in FIG.
2
E. Then, the backward delay circuit
14
sequentially delays the output signal locked in the mirror control circuit
13
, and outputs the delayed locking signal DS
12
as shown in FIG.
2
F.
The second delay array
16
receiving the delayed locking signal DS
12
, as show in
FIG. 2G
, delays the output signal of the mirror control circuit
13
by time period t
4
, and delays the delayed locking signal DS
12
before the third clock signal CK of the clock signal CK is outputted and then outputs the negative delay signal CKO.
The conventional negative delay signal generation circuit as described above may utilize the negative signal generated by receiving the clock signal as a system internal clock signal when the input signal is in a high frequency. However, the conventional negative delay signal generation circuit disadvantageously fails to output a negative delay signal because the mirror control circuit
13
for receiving the output signal of the forward delay circuit and the one shot pulse signal outputted from the pulse generator causes timing skew for thereby being unable to output a locked signal to the backward delay circuit.
Therefore, an additional circuit should be provided in order to test a semiconductor chip operation in a low frequency by use of the conventional negative delay signal generation circuit, thereby incurring an increased circuit size and complication.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming the conventional disadvantages.
Therefore, it is an object of the present invention to provide a low frequency detection circuit for using a negative delay signal as a system internal clock signal when a clock signal is in high frequency, and using the clock signal as a system internal clock signal when the clock signal is in low frequency.
To achieve the above-described object, there is provided a low frequency detection circuit according to the present invention which includes a negative delay signal generator for receiving an input signal and outputting a negative delay signal and a plurality of low frequency detection signals, a low frequency detector for receiving the plurality of low frequency detection signals and outputting a flag signal, and a signal selector for outputting one selected from the input signal and the negative delay signal in accordance with the flag signal.
The object and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 4618787 (1986-10-01), Jacksier et al.
patent: 5440592 (1995-08-01), Ellis et al.
patent:

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