Low frequency clock feed-through charge pump circuit

Details Low frequency clock feed-through charge pump circuit Low frequency clock feed-through charge pump circuit

2000-04-28

2001-09-04

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S536000

Reexamination Certificate

active

06285224

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88113215, filed Aug. 3, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a phase locked loop (PLL) circuit, and in particular to a charge pump circuit in a phase locked loop circuit.
2. Description of the Related Art
In line with the great progress in semiconductor technology, the operating speed of contemporary computers is getting increasingly fast. However, higher operating frequency causes more power consumption. In order to reduce the unnecessary power consumption, it is designed to reduce the operating voltage of computers from 5V to 3.3V, then further to 2.5V, even to less than 2.0V. In coordination with the decrease of operating voltage, it is necessary to modify a great number of circuits, such as an oscillator for providing a clock signal. In a current computer system, there is simultaneously a variety of clock frequencies. Generally, a phase locked loop circuit is used to generate a number of clock signals with different proportional frequencies on with respect to a reference clock signal for the uses of a plurality of sub-systems. Moreover, a voltage control oscillator is a main factor to affect the performance of the phase locked loop circuit. And, the performance of the voltage control oscillator depends on its own long term jitter and short term jitter and the variation of a power supply voltage.
FIG. 1
is a block circuit diagram showing a conventional phase locked loop circuit. Referring to
FIG. 1
, a phase locked loop circuit includes a phase detector
10
, a charge pump
12
, a lowpass filter (LPF)
14
and a voltage control oscillator (VCO)
16
. In general, the less the fluctuation of the input voltage signal of the voltage control oscillator
16
, the less the jitter of the output voltage. As a result, the phase locked loop circuit can have an output voltage with a stable frequency. To minimize the fluctuation of the voltage signal input to the voltage control oscillator
16
, it is necessary to make two current sources located in the charge pump
12
have the same current flow.
FIG. 2
is a circuit diagram showing the charge pump
12
of FIG.
1
. Referring to
FIG. 2
, switches SW
1
, SW {overscore (
1
)}, SW
2
, SW {overscore (
2
)} consist of transistors which all operate in a linear region. When each transistor is turned off from an on-state, charges stored on the drain must be released, causing charge injection. The less the charges stored on the drain, the less the effect of the charge injection. As a result, the control voltage of the VCO
16
almost remains unchanged. Since the SW {overscore (
1
)} and SW {overscore (
2
)} operate in the linear region, charges are accumulated in their channels between on-state and off-state thereof. Most charges stored around the drain can be released, resulting in an effect on the output voltage.
A current is mirrored into a transistor T
2
and a current source
12
by a transistor Q. Therefore, if the voltage on a node P
3
is equal to that on a node P
4
, it can make the current source
12
have the same current flow as the transistor T
2
. Assume that the voltage on the node P
4
is at a certain constant value. If the voltage on the node P
3
is larger than that on the P
4
, the current I
1
is slightly larger than the current I
2
as a result of channel modulation. Nevertheless, the voltage on a node P
2
must be larger than the voltage on the node P
4
. Since the gate and the drain of the transistor T
1
are electrically coupled to each other to form a diode, it makes the transistor T
1
have a current flow different from the transistor T
2
if the voltage of the node P
2
is equal to the voltage of the node P
4
. In addition, since the current of a current source I
3
is mirrored by the transistor T
1
, the current source I
3
has the same current flow as the transistor T
1
. As a whole, the current flows of the current source I
2
and current source I
3
are different in value. Typically, the current source I
3
has a larger current flow than the current source I
2
. If the difference of the current flows of the current sources I
2
, I
3
is larger, the fluctuation of the voltage becomes much larger. As a result, the jitter of the output voltage of the voltage control oscillator
14
becomes more serious.
Moreover, since the transistors operating in the linear region can be considered as resistors, the voltage variation of the output points will affect the nodes P
1
, P
4
so as to change the values of the I
2
and I
3
.
SUMMARY OF THE INVENTION
In view of the above, an object of the invention is to provide a low clock feed through charge pump circuit which includes a plurality of switch transistors, wherein the transistors all operate in a saturation region to thereby prevent charge injection occurring on the switch transistors of the charge pump circuit.
Another object of the invention is to provide a low clock feed through charge pump circuit which can greatly reduce the fluctuation of a signal input to a voltage control oscillator, thereby lowering the jitter of the output signal of the voltage control oscillator and stabilizing the frequency of the output signal of the phase locked loop circuit.
The low clock feed through charge pump circuit of the invention includes a first pump transistor, a second pump transistor, a first switch device, a second switch device, a third switch device, a fourth switch device, a first cascode transistor circuit, a second cascode transistor circuit, a third cascode transistor circuit, a fourth cascode transistor, a first wide-swing current mirror and a second wide-swing current mirror. The source of the first pump transistor is electrically coupled to a power supply while the source of the second pump transistor is electrically coupled to ground, wherein the first pump transistor and the second pump transistor each serves as a current source. Each of the first switch device, the second switch device, the third switch device and the fourth switch device has a first terminal, a second terminal and a third terminal. The first terminals of the first switch device and the second switch device are electrically coupled to the drain of the first pump transistor. The second terminals of the third switch device and the fourth switch device are electrically coupled to the drain of the second pump transistor. The second terminals of the first switch device and the second switch device are electrically coupled to the first terminals of the third switch device and the fourth switch device, respectively. The third terminals of the first switch device and the second switch device are electrically coupled to each other while the third terminals of the third switch device and the fourth switch device are electrically coupled to each other. The two wide-swing current mirrors are used to provide a bias required by the low clock feed through pump circuit and have a more precise current generated than a conventional bias circuit and a low voltage source than a general cascode current mirror. The first wide-swing current mirror , mainly a cascode transistor circuit, is electrically coupled between the power supply and ground and consists of two transistors, wherein the first transistor has its gate electrically coupled to the third terminal of the first switch device and the second transistor has its gate electrically coupled to the gate of the first pump transistor and the drain of the first transistor. The second wide-swing current mirror, mainly a cascode transistor circuit, consists of two transistors, wherein the first has its gate electrically coupled to the third of the fourth switch device and the other has its gate electrically coupled to the gate of the second pump transistor and the drain of the first transistor. The second wide-swing current mirror also provides the first wide-swing current mirror a required bias current. An input current is electrically coupled to the drain of the first transistor and the gate of the second tr

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