Low-error canonic-signed-digit fixed-width multiplier, and...

Details Low-error canonic-signed-digit fixed-width multiplier, and... Low-error canonic-signed-digit fixed-width multiplier, and...

2006-07-18

2006-07-18

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S550000

Reexamination Certificate

active

07080115

ABSTRACT:
An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.

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