Low dropout voltage regulator with variable bandwidth based...

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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Details

C323S280000

Reexamination Certificate

active

06465994

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to low dropout voltage regulators with variable bandwidth based on load current.
BACKGROUND OF THE INVENTION
A prior art general architecture of an internal compensated low dropout voltage regulator (LDO) is shown in FIG.
1
. This LDO includes an error amplifier A
1
, a wide band gain stage A
2
for better pole-splitting, a buffer BUF for impedance translation, an internal compensation cap Cc, a feedback resistor string R
1
and R
2
, and an output power PMOS transistor PSW (power switch). The LDO also includes reference voltage VREF; bias voltage VBIAS; source voltage VDD; feedback voltage VFB; output current Iout; output voltage VOUT; equivalent series resistor (ESR) R_ESR; output filter capacitor C_FILT; and external load LOAD. If designed properly, the bandwidth, pole position of this LDO can be calculated by simply applying two stage amplifier equations a shown in the equations below.
Dominant



pole

:



f
Pd
=
1
2

π
·
(
1
+
A2
·
G
mPSW
·
r
oPSW
)
·
r
oA1
·
C
c
(
1
)
Second



pole

:



f
P2
=
A2
·
G
mPSW
2

π
·
C
FILT
(
2
)
Open



loop



unity



gain



bandwidth

:



f
UGBol
=
g
mA1
2

π
·
C
C
·
R
2
R
1
+
R
2
(
3
)
where G
mPSW
is the transconductance of transistor PSW; A
2
is the gain of amplifier A
2
; Cc is the capacitance of capacitor Cc; r
oA1
is the output impedance of amplifier A
1
; r
oPSW
is the output impedance of transistor PSW; C
FILT
is the capacitance of capacitor C_FILT; and g
mA1
is the transconductance amplifier A
1
.
To satisfy stability criteria, the second pole f
P2
needs to be pushed close to or beyond the unity gain bandwidth f
UGBol
. As we can see from equation (2), the second pole f
P2
moves with the transconductance of the power PMOS PSW, g
mPSW
, which is proportional to {square root over (I
OUT
)}. For an LDO, the output current ranges from a few uA's to hundreds of mA's, thus the transconductance g
mPSW
changes 2-3 decades and so does the second pole f
P2
. For a conventionally designed LDO, the bandwidth f
uGBol
is limited by the worst-case second pole f
P2
where output current I
OUT
is minimum.
SUMMARY OF THE INVENTION
A low dropout voltage regulator includes: a first amplifier having a reference voltage node coupled to a first input; a second amplifier having an input coupled to an output of the first amplifier; a variable bias current source coupled to the first amplifier and having a control node coupled to an output of the second amplifier; a power switch having a control node coupled to the output of the second amplifier and having a first end coupled to a source voltage node; and a feedback circuit having an input coupled to a second end of the power switch and an output coupled to a second input of the first amplifier. The best node in the system that detects the load current level is the output of the second amplifier. This signal is used to modulate the bias current of the first amplifier by increasing the bias current when the load current increases and vice versa, which consequently modulates the transconductance of the first amplifier. This provides a higher bandwidth LDO with better transient performance and higher power supply rejection ratio.


REFERENCES:
patent: 5648718 (1997-07-01), Edwards
patent: 5686820 (1997-11-01), Riggio, Jr.
patent: 5686821 (1997-11-01), Brokaw
patent: 5864227 (1999-01-01), Borden et al.
patent: 5889393 (1999-03-01), Wrathall
patent: 6046577 (2000-04-01), Rincon-Mora et al.
patent: 6201375 (2001-03-01), Larson et al.
patent: 6333623 (2001-12-01), Heisley et al.
patent: 6373233 (2002-04-01), Bakker et al.

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