Low dropout voltage regulator with non-miller frequency...

Details Low dropout voltage regulator with non-miller frequency... Low dropout voltage regulator with non-miller frequency...

2001-09-28

2003-02-11

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

06518737

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to low dropout voltage regulators, and in particular, to those built in biCMOS and CMOS processes.
2. Description of the Related Art
Low dropout voltage regulators (LDOs) are used in power supply systems to provide a regulated voltage at a predetermined multiple of a reference voltage. LDOs have emerged as front-line integrated circuits (ICs) in the last decade, being used in palmtop and laptop computers, portable phones, and other entertainment and business products. Due to the growing need to save power, all battery-operated electronic systems use or will probably use LDOs with low ground current. More and more LDOs are built in bipolar complementary metal oxide semiconductor (biCMOS) and enhanced CMOS processes, which may provide a better, but not always cheaper product.
FIG. 1
is a simplified block diagram of a conventional CMOS low dropout positive voltage regulator LDO
10
, which is based on FIGS. 2 and 3 of U.S. Pat. No. 5,563,501 (Chan). An unregulated input voltage VIN is applied to an input terminal
12
. A bandgap reference
14
delivers a desired reference voltage to an inverting input line
16
of an error amplifier
18
, which is an operational transconductance amplifier (OTA). A non-inverting input line
20
of the amplifier
18
is connected to the output of a negative feedback network (resistors R
1
30
and R
2
32
). An output line
21
of the error amplifier
18
is coupled to the input of a buffer
22
.
The buffer
22
in
FIG. 1
is a voltage follower with an output stage (M24, M25, Q17, Q18 in FIG. 4 of U.S. Pat. No. 5,563,501) that provides a low output impedance to line
23
, which is coupled to a high parasitic capacitance gate of a power p-channel metal oxide semiconductor (PMOS) path transistor
24
(path element). The power transistor
24
has its drain connected to an output terminal
26
, where a regulated output voltage VOUT is available. The feedback network (R
1
30
and R
2
32
) is a voltage divider, which establishes the value of VOUT. The feedback network consists of an upper resistor R
1
30
connected between the output rail
26
and a node N
1
, and a lower resistor R
2
32
connected between node N
1
and a ground terminal
28
.
As described in U.S. Pat. No. 5,563,501 (col. 1), a desirable LDO may have as small a dropout voltage as possible, where the “dropout voltage” is the voltage drop across the path element (power PMOS transistor
24
in FIG.
1
), to maximize DC performance and to provide an efficient power system. To achieve a low dropout voltage, it is desirable to maximize the channel-width-to-channel-length ratio of the power PMOS transistor
24
, which leads to a larger area and a large parasitic capacitance between gate and drain/source of the power PMOS transistor
24
. Such large PMOS transistors, having a large parasitic capacitance between the gate and the drain/source, makes frequency compensation more difficult, affecting the transient response and permitting a high frequency input ripple to flow to the output.
Being a negative feedback system, an LDO needs frequency compensation to keep the LDO from oscillating. The LDO
10
in
FIG. 1
performs frequency compensation by using an internal Miller compensation capacitor
34
, which is connected through additional circuitry
36
between the output terminal
26
and line
21
. In U.S. Pat. No. 5,563,501, the additional circuitry 36 is a current follower. The frequency compensation arrangement of the LDO
10
in
FIG. 1
permits the use of a single, low-value external capacitor
40
, having a low equivalent series resistance (ESR)
42
, which may be intrinsically or externally added.
The buffer
22
in
FIG. 1
is built using a foldback cascode operational amplifier with NPN input transistors and an NPN common-collector output stage. However, these NPN transistors are not available in standard digital N-well CMOS processes.
In another LDO disclosed in U.S. Pat. No. 6,046,577 (Rincon-Mora), the buffer
22
is built in a biCMOS process using two cascaded stages: a common-collector NPN voltage follower and a common-drain PMOS voltage follower.
G. A. Rincon-Mora discloses another solution for the buffer
22
in a paper entitled “Active Capacitor Multiplier in Miller-Compensated Circuits,” IEEE J. Solid-State Circuits, vol. 35, pp. 26-32, January 2000, by replacing the first NPN stage with a common-drain NMOS, thus being closer to a CMOS process. Nevertheless, in order to eliminate the influence of bulk effects on the NMOS stage (for N-well processes), which affects power supply rejection ratio (PSRR), additional deep n+ trench diffusion and buried n+ layers are needed.
The frequency compensation used in the Rincon-Mora paper mentioned above is the same as that disclosed in U.S. Pat. No. 6,084,475 (Rincon-Mora), and is close to that of FIG.
1
. The difference is that the Miller compensation capacitor
34
is connected between the output terminal
26
and an internal node of the error amplifier
18
, as shown by the dotted line in FIG.
1
. In this configuration, no additional circuitry
36
is needed.
SUMMARY OF THE INVENTION
The LDOs described above have several drawbacks, including: (1) the use of expensive biCMOS or enhanced CMOS processes, (2) limited closed-loop bandwidth, e.g., under 100 KHz, which may be caused by the output stage (M24, M25, Q17, Q18 in FIG. 4 of U.S. Pat. No. 5,563,501) in the buffer
22
of
FIG. 1
or caused by other circuit elements, (3) non-ideal transient response, even at low ESR, due to a low slew-rate (SR) (maximum possible rate of change) provided for the internal capacitor
34
and/or due to the output stage (M24, M25, Q17, Q18 in FIG. 4 of U.S. Pat. No. 5,563,501) in the buffer
22
of
FIG. 1
or due to other circuit elements, and (4) poor power supply rejection ratio (PSRR)(rejection of noise) at high frequency. Some of these limitations are disclosed in Rincon-Mora's paper (see FIGS. 1 through 9).
A low dropout voltage regulator with non-Miller frequency compensation is provided in accordance with the present invention The low dropout voltage regulator comprises a first operational transconductance amplifier (OTA), a second OTA, a power p-channel metal oxide semiconductor (PMOS) transistor, and a feedback network The first OTA has an inverting input, a non-inverting input and an output. The inverting input is coupled to a voltage The non-inverting input is coupled to a feedback network The first OTA is configured to operate as an error amplifier. The second OTA has an inverting input, a non-inverting input and an output. The non-inverting input is coupled to the output of the first OTA. The output of the second OTA is coupled to the inverting input of the second OTA to form a voltage follower.
The power PMOS transistor has a source terminal, a drain terminal and a gate terminal. The source terminal is coupled to an input voltage terminal The gate terminal is coupled to the output of the second OTA. The drain terminal is coupled to an output voltage terminal. The feedback network comprises a first resistor, a second resistor, and a frequency compensation capacitor. The first and second resistors are coupled in series between the output voltage terminal and a ground terminal The frequency compensation capacitor is connected in parallel with the first (upper) resistor of the feedback network. The non-inverting input of the first OTA is coupled to a first node between the first and second resistors.
In order to optimize frequency compensation and transient response, by eliminating the need for a Miller compensation capacitor, both OTAs are designed with wide-band and low-power (low-current) circuit techniques. These wide-band, low-power OTAs enable the use, in addition to the single frequency compensation capacitor, of a single, low-value load capacitor with a low-value, intrinsic equivalent series resistance (ESR).
Some conventional LDOs need high-value, eternally-added ESRs to become stable. An LDO using a high-value ESR has the main disadvantag

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