Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-03-19
2003-04-01
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S281000, C323S274000
Reexamination Certificate
active
06541946
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to low dropout voltage regulators with improved power supply rejection ratios.
BACKGROUND OF THE INVENTION
Low dropout voltage regulators (LDO) are widely used to step down battery voltage and suppress voltage disturbances from batteries or switching regulators in portable electronics equipment, such as cellular phones, MP
3
, and digital cameras. Power supply rejection ratio (PSRR) of the LDO, defined as the capability of rejecting input supply voltage ripple at the output of the LDO, is a very important requirement in LDO design.
A conventional prior art LDO is shown in FIG.
1
. The prior art circuit includes error amplifier
20
; amplifier
22
; PMOS pass transistor
24
; feedback resistors
26
and
28
; load resistance
30
; load capacitance
32
; supply voltage V
in
; reference voltage V
ref
; and output voltage V
o
. In many conventional LDO designs, such as the prior art LDO shown in
FIG. 1
, power supply disturbance is suppressed by a negative feedback circuit consisting of an error amplifier
20
, amplifier
22
, and pass transistor
24
. The PSRR is mainly determined by the open-loop gain of amplifier
20
, amplifier
22
, and pass transistor
24
, and position of internal poles. The conventional prior art LDO suffers from an inherent PSRR performance limitation due to the continuous roll-off of open-loop gain with increasing frequency and limited bandwidth of the error amplifier
20
. Therefore, to design a high-PSRR LDO, a control loop with high gain and high bandwidth is needed, which, however, sometimes conflicts with other requirements such as stability and current consumption.
SUMMARY OF THE INVENTION
A low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier having a first input coupled to a reference voltage node; a second amplifier having an input coupled to an output of the first amplifier; a pass transistor having a control node coupled to an output of the second amplifier; a feedback circuit having an input coupled to the pass transistor and an output coupled to a second input of the first amplifier; an inverting gain stage coupled to the input of the second amplifier; and a high pass filter coupled between a power supply node and a control node of the inverting gain stage. The circuit uses the high pass filter and inverting gain stage to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node.
REFERENCES:
patent: 6300749 (2001-10-01), Castelli et al.
patent: 6465994 (2002-10-01), Xi
Chen Jun
Xi Xiaoyu
Brady III W. James
Riley Shawn
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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