Low dropout voltage reference

Details Low dropout voltage reference Low dropout voltage reference

1999-10-13

2001-03-06

Wong, Peter S. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S275000, C323S280000

Reexamination Certificate

active

06198266

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is related to U.S. patent application Ser. No. 09/416,899, entitled “CMOS VOLTAGE REFERENCE WITH A NULLING AMPLIFIER”, filed Oct. 13, 1999; U.S. patent application Ser. No. 09/416,896, entitled “SLOPE AND LEVEL TRIM DAC FOR VOLTAGE REFERENCE”, filed Oct. 13, 1999; and U.S. patent application Ser. No. 09/416,897, entitled “CMOS VOLTAGE REFERENCE WITH POST ASSEMBLY CURVATURE TRIM”, filed Oct. 13, 1999; all applications are commonly assigned to the assignee of the present invention, and the disclosures of which are herein incorporated by reference.
1. Field of the Invention
The present invention relates generally to the field of low dropout references, and more particularly to a low dropout reference amplifier circuit that is stable under various load conditions.
2. Description of the Related Art
FIG.
1
(A) is a block diagram of a conventional low dropout (LDO) voltage reference. The stability of this type of LDO reference is highly dependent on the load attached to Vout. This load dependence is due to the high impedance of the drain terminal of the p-channel output pass FET M
11
that results in a low frequency pole, which introduces a phase shift in the feedback loop. In addition to the stability problems, the line regulation of the conventional reference is poor due in part to the fact that the drain voltages of the cascode p-channel FETs M
5
, M
6
are not constant under all operating conditions. The drain voltage variance results in a differential error current due to the Early effect and/or unbalanced leakage currents from the drain to well junctions. The differential error current will produce an input referred offset error that is power supply dependent. FIG.
1
(B) is a schematic of a typical implementation of the conventional LDO circuit of FIG.
1
(A).
A low dropout voltage regulator is disclosed in U.S. Pat. No. 5,672,959, entitled “LOW DROP-OUT VOLTAGE REGULATOR HAVING HIGH RIPPLE REJECTION AND LOW POWER CONSUMPTION.” The disclosed circuit relies on an external load capacitance to stabilize one of the two feedback loops. This has a similar disadvantage in that the circuit performance is dependent upon the load.
In view of the foregoing, it would be desirable to have a low dropout voltage reference that is stable under various loading conditions and has improved power supply rejection.
SUMMARY OF THE INVENTION
The present invention is a low dropout voltage reference having three gain stages and two feedback loops, an overall loop and a secondary loop. The overall feedback loop establishes a desired output voltage. The secondary feedback loop provides two benefits: (1) a broadband reduction of the output impedance to ensure stability under various loading conditions and (2) an improvement in power supply rejection. The first benefit ensures that the pole created by the load capacitance and the output impedance of the amplifier doesn't adversely affect the overall loop stability. The second benefit helps improve line regulation.
The low dropout voltage reference does not rely on a capacitor connected to the output to properly compensate the overall feedback loop. Therefore, the reference will work properly for a wide range of load capacitance values. Also, the present invention may be manufactured in CMOS, reducing the manufacturing costs associated with bipolar designs.
The present invention incorporates a band-gap core to provide temperature compensation, and in one embodiment uses a differential input stage, an Output Transconductance Amplifier (OTA) and an output MOSFET. Also, a unique compensation scheme for the overall feedback loop is disclosed.


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