Low drop-out voltage regulator

Details Low drop-out voltage regulator Low drop-out voltage regulator

2002-10-24

2004-03-09

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S276000, C323S303000

Reexamination Certificate

active

06703813

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to voltage regulators. More particularly, the present invention is related to a low drop-out voltage regulator that is tolerant to input voltages that exceed the maximum permissible voltage of the individual pass transistors.
BACKGROUND OF THE INVENTION
Voltage regulators are often used to provide a relatively constant voltage source to other electronic circuits. Some regulators are limited in their effectiveness in a particular application. For example, some regulators have a high “drop-out” voltage. A “drop-out” voltage is the minimum voltage difference between the input voltage and the output voltage that is necessary to maintain proper regulation. Large drop-out voltages result in wasted power, and raise the minimum power supply requirements for maintaining regulation.
A low drop-out regulator (hereinafter referred to as an “LDO regulator”) is useful in applications where it is desired to maintain a regulated voltage that is sufficiently close to the input voltage. For example, LDO regulators are useful in battery-powered applications where the power supply voltage is exceedingly low.
A typical LDO regulator (
400
) is shown in FIG.
4
. The LDO regulator (
400
) includes a PMOS transistor (MP
40
), a first resistor (R
41
), a second resistor (R
42
), and a voltage control block (
410
). The PMOS transistor (MP
40
) has a drain that is connected to an output terminal (VREG), a gate that is connected to node N
40
, and a source that is connected to an input voltage (VIN). The first resistor (R
41
) is series connected between the output terminal (VREG) and node N
41
. The second resistor (R
42
) is series connected between node N
41
and a circuit ground (GND). The voltage control block (
410
) has three input terminals (VIN, VREF, SENSE) and an output terminal (PCTL). In the voltage control block (
410
), the first input terminal (VIN) is connected to the input voltage (VIN), the second input terminal (VREF) is connected to a reference voltage (VREF), and the third input terminal (SENSE) is connected to node N
41
. The output terminal (PCTL) of the voltage control block (
410
) is connected to node N
40
.
A load (ZL) is connected to the output terminal (VREG) of the LDO regulator (
400
). The LDO regulator (
400
) controls the gate of the PMOS transistor (MP
40
) to ensure that regulation of the output voltage (VREG) is maintained. The voltage control block (
410
) monitors the SENSE input terminal and controls the gate of the PMOS transistor (MP
40
) through the PCTL output terminal. Resistors R
41
and R
42
form a resistor divider that produces a signal that is related to the regulated output voltage (VREG). When the SENSE input terminal and the reference signal (VREF) are substantially the same, the LDO is properly maintaining regulation of the output voltage to the load (ZL).
SUMMARY OF THE INVENTION
Briefly stated, the present invention is related to an LDO regulator that provides regulation of an output voltage at an output node. The LDO regulator includes a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.


REFERENCES:
patent: 4864213 (1989-09-01), Kido
patent: 5036269 (1991-07-01), Murari et al.
patent: 6373233 (2002-04-01), Bakker et al.
patent: 6377131 (2002-04-01), Langer
patent: 6380721 (2002-04-01), Pattamatta et al.
patent: 6600297 (2003-07-01), Takeda et al.

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