Low drop-out regulator

Details Low drop-out regulator Low drop-out regulator

2002-10-01

2004-07-06

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S284000, C323S901000

Reexamination Certificate

active

06759836

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to voltage regulators. More particularly, the present invention is related to a circuit for improving power-on speed and power supply rejection ratio (PSRR) characteristics for a low drop out voltage (LDO) regulator.
BACKGROUND OF THE INVENTION
Voltage regulators are often used to provide a relatively constant voltage source to other electronic circuits. Some regulators are limited in their effectiveness in a particular application. For example, some regulators have a high “drop-out” voltage. A “drop-out” voltage is the minimum voltage difference between the input voltage and the output voltage that is necessary to maintain proper regulation. Large drop-out voltages result in wasted power, and raise the minimum power supply requirements for maintaining regulation.
A low-drop-out regulator (hereinafter referred to as an “LDO regulator”) is useful in applications where it is desired to maintain a regulated voltage that is sufficiently close to the input voltage. For example, LDO regulators are useful in battery-powered applications where the power supply voltage is exceedingly low.
A typical LDO regulator (
500
) is shown in FIG.
5
. The LDO regulator (
500
) includes a PMOS transistor (MP
50
), a first resistor (R
50
), a second resistor (R
51
), and a voltage control block (
510
). The PMOS transistor (MP
50
) has a drain that is connected to an output terminal (VREG), a gate that is connected to node N
50
, and a source that is connected to an input voltage (VIN). The first resistor (R
51
) is series connected between the output terminal (VREG) and node N
51
. The second resistor (R
52
) is series connected between node N
51
and a circuit ground (GND). The voltage control block (
510
) has three input terminals (VIN, VREF, SENSE) and an output terminal (PCTL). In the voltage control block (
510
), the first input terminal (VIN) is connected to the input voltage (VIN), the second input terminal (VREF) is connected to a reference voltage (VREF), and the third input terminal (SENSE) is connected to node N
51
. The output terminal (PCTL) of the voltage control block (
510
) is connected to node N
50
.
A load (ZL) is connected to the output terminal (VREG) of the LDO regulator (
500
). The LDO regulator (
500
) controls the gate of the PMOS transistor (MP
50
) to ensure that regulation of the output voltage (VREG) is maintained. The voltage control block (
510
) monitors the SENSE input terminal and controls the gate of the PMOS transistor (MP
50
) through the PCTL output terminal. Resistors R
51
and R
52
form a resistor divider that produces a signal that is related to the regulated output voltage (VREG). When the SENSE input terminal and the reference signal (VREF) are substantially the same, the LDO is properly maintaining regulation of the output voltage to the load (ZL).
SUMMARY OF THE INVENTION
Briefly stated, the present invention is arranged to provide an enhanced power-on speed for a low drop-out (LDO) voltage regulator while improving power supply rejection ratio (PSRR) performance. A first capacitive circuit is coupled to the output of the LDO regulator. A second capacitive is selectively coupled to a power supply signal circuit and arranged to store charge when the LDO regulator is deactivated. When the LDO regulator is activated, a portion of the charge on the second capacitive circuit is transferred to the first capacitive circuit. The configuration decreases the power-on time of the LDO regulator, and provides for improved PSRR characteristics.
In accordance with the present invention, an apparatus for providing improved power-on speed and power supply rejection ratio (PSRR) characteristics for a low drop-out (LDO) voltage regulator includes a low drop-out (LDO) voltage regulator that is configured to provide an output voltage to an output when activated. A first capacitive circuit is coupled to the output of the low drop-out (LDO) voltage regulator. A second capacitive circuit is selectively coupled to a power supply during a first cycle and selectively coupled to the first capacitive circuit during a second cycle. The first cycle corresponds to when the low drop-out (LDO) voltage regulator is deactivated, and the second cycle corresponds to when the low drop-out (LDO) voltage regulator is activated.
In accordance with another aspect of the invention, a first switch circuit is coupled between the second capacitive circuit and the power supply. A second switch circuit is coupled between the first capacitive circuit and the second capacitive circuit. The first switch circuit is closed and the second switch circuit is open during the first cycle. The first switch circuit is open and the second switch circuit is closed during the second cycle. A first resistor is coupled between the first switch circuit and the power supply. Current is provided to the second capacitive circuit across the first resistor when the first switch circuit is closed. The first switch circuit is responsive to a first control signal and the second switch circuit is responsive to a second control signal.
The invention may also be implemented as methods that perform substantially the same functionality as the embodiments of the invention discussed above and below.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.


REFERENCES:
patent: 5973944 (1999-10-01), Nork
patent: 6603292 (2003-08-01), Schouten et al.

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