Low divide ratio programmable frequency divider and method...

Details Low divide ratio programmable frequency divider and method... Low divide ratio programmable frequency divider and method...

2007-10-16

2007-10-16

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000

Reexamination Certificate

active

11380917

ABSTRACT:
The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.

REFERENCES:
patent: 6219397 (2001-04-01), Park
patent: 6369623 (2002-04-01), Heinen

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