Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-06-29
2002-03-05
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000
Reexamination Certificate
active
06353405
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an analog-to-digital (A/D) converter for image sensors. More particularly, the present invention relates to a low distortion video A/D converter for image sensor interfaces.
2. Description of Related Art
For general imaging applications, such as scanners, images from charge couple device (CCD) have to be processed to compensate for non-uniform illumination of a subject. In order to obtain a correct two-dimensional picture from the CCD signal, several corrections or adjustments must be performed. For example, gain and offset corrections account for the difference in sensitivity between red, green and blue signals. A video A/D converter is used not only for converting the analog image signal to a digital signal, but also performing these corrections and adjustments.
FIG. 1
shows a conventional block diagram of a video A/D converter. The video A/D converter comprises a correlated double sampling (CDS) module, an A/D converter (ADC)
110
, a DC restoring circuit
120
, and a plurality of adjustment circuits
130
,
140
,
150
and a timing control circuit
160
.
A typical CDS module
100
is illustrated in
FIG. 2
for discussion of its operations. Referring to
FIG. 2
, the CDS module
100
comprises three CDS circuits and a 3-to-1 multiplexer
108
. All of the three CDS circuits have the same structure. Taking the first CDS circuit for sampling the analog red signal V
R
as an example, the first CDS comprises a first sample/hold circuit
104
a
, a second sample/hold circuit
104
b
and a differential amplifier
106
a
. The first sample/hold circuit
104
a is driven by a control signal Vs and the second sample/hold
104
b
is driven by a control signal Rs. The analog red signal V
R
from a CCD is inputted to the first and the second sample/hold circuits
104
a
/
104
b
through a capacitor C
R
.
The conventional CDS module uses three CDS circuits to sample the red, green and blue signals V
R
, V
G
and V
B
simultaneously. Accordingly, a signal Sc is simultaneously applied to the analog switches
102
a
,
102
b
and
102
c
to clamp simultaneously the capacitors C
R
, C
G
and C
B
to a reset level (voltage V
x
). The control signals Vs and Rs activate the sample/hold circuits
104
a
/
104
b
for sampling the red signal V
R
, the sample/hold circuits
104
c
/
104
d
for sampling the green signal V
G
, and the sample/hold circuits
104
e
/
104
f
for sampling the blue signal V
B
. The control signal Vs is applied to all of the first sample/hold circuits
104
a
/
104
c
/
104
e
, and the control signal Rs is applied to all of the second sample/hold circuits
104
b
/
104
d
/
104
f.
After the analog switches
102
a
/
102
b
/
102
c
are disabled, the sample/hold circuits
104
a
/
104
b
,
104
c
/
104
d
, and
104
e
/
104
f
begin to sample the red, green, and blue signal V
R
, V
G
, and V
B
respectively in response to the control signals Rs, Vs. As shown in
FIG. 3
, the sample/hold circuit
104
b
begins to sample the red signal V
R
, obtaining a reset level voltage V
1
, when the control signal Rs is transient to high, while the sample/hold circuit
104
a
begins to sample the red signal V
R
, obtaining a video signal voltage V
2
when the control signal Vs is transient to high. Thereafter, the differential amplifier
106
a
receives the two input signals V
1
and V
2
, and then outputs the result to the multiplexer
108
. The operations for sampling the green and blue signals V
G
and V
B
are the same. The multiplexer
108
then selects one of the outputs of the differential amplifier
106
a
,
106
b
and
106
c
and outputs an amplified signal V
A
to the ADC
110
at each clock period.
For the reasons discussed above, the conventional CDS module uses three CDS circuits for sampling the red, green and blue signals V
R
, V
G
and V
B
simultaneously, and consequently the noise level is high and an electric magnetic interference (EMI) problem always occur.
In addition, a practical problem with the CDS circuit is that the output node of the differential amplifier slews back and forth between a video signal level and an initialized reset level at each clock period. This increases a settling time of the differential amplifier. Furthermore, this slew back and forth phenomenon also causes signal distortions.
Referring to
FIG. 1
again, the outputted signal V
A
from the CDS module
100
is then received by the ADC
100
for converting the analog signal V
A
to a digital signal first according to a constant reference voltage V
REF
. For example, when the ADC
110
outputs a digital red signal, the multiplexer
122
selects a DC bias from the red register
124
a
to the DC restoring circuit
120
, the DC restoring circuit
120
then adds the DC bias to the digital red signal. Thereafter, the gain adjustment circuit
130
adjusts the gain of the digital red signal by multiplying a gain value selected by the multiplexer
132
from the red register
134
a
. The offset adjustment circuit
140
and shading adjustment circuit
150
then adjust the offset and shading of the digital red signal by multiplying an offset and a shading value respectively selected by the multiplexers
142
,
152
from the red registers
144
a
,
154
a.
Therefore, from the discussion above, the video signal is converted to digital in advance, and a number of adjustment operations, such as DC restoration, gain adjustment, offset adjustment and shading adjustment, are then performed in the digital domain. The majority of these adjustments are multiplication operations. However, due to the current technological limitations in speed and resolution, the data length (x-bit) of the digital output is limited to such as 12-bit, 14-bit or 16-bit, etc. Therefore, after each adjustment operation is performed, the generated data length is increased due to the multiplications, and must be truncated to meet data length requirement. The outputted signal is then distorted.
Accordingly, for the reasons discussed above, the conventional video A/D converter has several shortcomings. For example, a larger noise level and an EMI problem occur because all of the prime signals are sampled simultaneously. The slew back and forth phenomenon of the CDS circuit also causes signal distortions. In addition, all of the adjustment operations are performed by multiplication in digital domain, the outputted signal is then distorted because truncation of the data is necessary in view of the data length requirement.
SUMMARY OF THE INVENTION
The invention provides a video analog-to-digital converter, comprising a differential correlated double sampling (DCDS) module, a DC bias circuit, an adjustment module and an analog-to-digital (A/D) converter. The DCDS module is used for sampling a red, a green, and a blue analog signal respectively with a delay time, and then selecting one of the sampled red, green and blue analog signals for outputting. The DC bias circuit is connected to the DCDS module for performing an analog addition to the output signal of the DCDS module for the DC bias restoration. The adjustment module is used for converting a set of digital adjustment data to an analog adjustable reference voltage The A/D converter is connected to the output of the DC bias circuit and the output of the adjustment module. By referring the adjustable reference voltage, the A/D converter converts the analog input signal to a digital output signal.
The DCDS module further comprises three DCDS circuits for sampling the red, the green and the blue analog signals respectively, time delay circuits connected between the DCDS circuits, and a multiplexer is used for selecting one of the sampled red, green and blue analog signals as an output signal.
Advantageously, the DCDS circuit can overcome the slew back and forth phenomenon of the conventional CDS circuit. In addition, the restoration of the DC bias and all of the adjustments are performed in the analog domain to avoid the truncation that causes signal distortion. Furthermore, the time delay circuits are used in the DCDS modul
Lin Jenn-yu G.
Yang Ta-yung
J. C. Patents
System General Corp.
Young Brian
LandOfFree
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