Low distortion sample and hold circuit

Details Low distortion sample and hold circuit Low distortion sample and hold circuit

2000-06-22

2001-11-27

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S091000, C327S093000

Reexamination Certificate

active

06323697

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to electronic circuits and specifically to a low distortion sample and hold circuit and method.
BACKGROUND OF THE INVENTION
A sample and hold circuit is a circuit that monitors a signal and provides a constant value at predetermined times. A block diagram of one such sample and hold circuit
10
is shown in FIG.
1
. This circuit
10
includes a switch
12
coupled in series with a capacitor
14
. In operation, the switch
12
is closed at the sample rate and the voltage across the hold capacitor
14
represents a first order held version of the input waveform V
in
. In CMOS technologies, this circuit is realized as a combination of MOS transistors.
FIG. 2
a
shows the schematic of an elementary NMOS sample and hold circuit
20
. In this implementation, switch
12
is an NMOS transistor
12
. The operation of a PMOS transistor is analogous and will not be discussed here.
FIG. 2
b
shows a timing diagram for a pulse &phgr;
1
that is applied to the gate of transistor
12
. When the gating waveform &phgr;
1
goes high (V
DD
), the switch
12
is on and the capacitor
14
is shorted to the input. When the input goes low (zero), the switch is off. As a result, the value of the input voltage V
in
will be held on the hold capacitor
14
.
While having the benefit of being simple in construction, the circuit of
FIG. 2
a
has a number of disadvantages. When the switch
12
is turned off, a part of the charge in the channel of the NMOS transistor
12
is dumped on to the hold capacitor
14
. Since this charge is signal dependent and nonlinear, this will cause distortion. In addition, the ON resistance of the switch
12
is signal dependent thereby causing further distortion. Also, the exact sampling instant of the switch is that time at which the gate-source voltage of the switch V
GS
is about equal to the transistor's threshold voltage V
T
. Since V
GS
=V
DD
−V
IN
, it is clear that the sampling instant is signal dependent. This too will cause significant distortion.
To mitigate some of the problems of the single channel MOS switch discussed above, bootstrapped switches have been proposed. The idea behind bootstrapping is to keep the gate source drive of the switch constant. This is done as shown in
FIG. 3
, which includes
FIGS. 3
a
and
3
b.
Referring first to
FIG. 3
a
, the circuit
30
includes a sample switch
12
, comprising an NMOS transistor, and a hold capacitor
14
. In this case, however, the gate of transistor
12
is coupled to a bootstrap circuit that includes bootstrap capacitor
32
and switches
34
-
37
.
FIG. 3
b
shows the timing of the waveforms &phgr;
1
and &phgr;
2
.
During the first phase, when &phgr;
1
is high, bootstrap capacitor
32
is charged to a bias voltage V
BIAS
. During the second phase, when &phgr;
2
is high, the bootstrap capacitor
32
is put across the gate and source terminals of switch
12
. This ensures that the V
GS
of the MOSFET is held constant at V
BIAS
irrespective of the input voltage Vet.
The channel charge is given by Q
ch
=C
ox
(V
BIAS
−V
T
(V
IN
)), where C
ox
is the capacitance across the gate oxide of transistor
12
and V
T
is the threshold voltage of transistor
12
, the voltage being a function of the input voltage V
IN
. From this relationship, it is thus seen that the inversion charge is substantially independent of the input voltage, except for a second order dependence through the threshold voltage.
This circuit, while exhibiting good performance, has a problem when implemented in an n-well technology. The channel charge Q
ch
, and thus the switch
12
resistance, depend on the input voltage V
IN
through the threshold V
T
. Accordingly, distortion will result.
This problem is solved by a modified arrangement proposed by Pan et al., “A 3.3V,
12
b
, 50 MSample/s A/D Converter in 0.6 &mgr;m CMOS with over 80 dB SFDR,” IEEE International Solid State Circuit Conference, Feb. 2000, pp. 40-41.
FIG. 4
a
illustrates such a circuit
40
and
FIG. 4
b
shows the corresponding waveforms.
The circuit
40
includes a sample switch
12
, comprising an NMOS transistor, and a hold capacitor
14
. The gate of transistor is coupled to switch
42
, which goes to ground, and switch
44
,
16
which goes to a voltage source V
bat
. In this arrangement, V
bat
is implemented as a switched capacitor level shifter. Transistor
46
is a replica of the switch device
12
. Operational amplifier
48
is coupled between V
bat
and the drain of replica transistor
46
. Current source
50
maintains a constant current through the transistor
46
.
In operation, replica transistor
46
operates in saturation. The gate of this transistor could exceed the supply voltage V
dd
. It is easily seen that if the operational amplifier is ideal, the potential at the gate of transistor
46
is given by V
IN
+V
T
(V
IN
+V
a
, and the channel charge is Q
ch
=C
ox
(V
a
), where V
a
is a constant voltage based on the VGS-VT of transistor
46
, which is dependent primarily on the current generated by current source
50
. Advantageously, the channel charge Q
ch
is independent of the input voltage V
IN
and body effect.
The circuit does, however, have a number of disadvantages. Transistor
46
operates in saturation while transistor
12
operates in the triode region. Thus, their respective threshold voltages may not be equal, especially in short channel technologies. Further, the transistor
46
is subject to large variations in drain source voltages. In short channel CMOS, this is a serious problem because of the modification of the threshold of transistor
46
through drain induced barrier lowering (DIBL). Finally, the operational amplifier
48
tends to consume a lot of power if fast settling is required. Incomplete settling of the operational amplifier reduces performance.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention provides a sample and hold circuit that overcomes many of the disadvantages of the prior art circuits.
In one aspect, the present invention contemplates a circuit that which can be used to perform a sample and hold function. This circuit includes a switch, such as a MOS transistor, coupled between an input node and an output node. A capacitor is coupled to the output node. A replica device is coupled between the input node and a supply voltage node. The circuit also includes a bootstrap circuit coupled between a control terminal of the first switch and a control terminal of the replica device.
In a more specific embodiment, a sample and hold circuit is disclosed. This circuit includes a sampling transistor with a current path coupled between an input node and an output node. A hold capacitor is coupled between the output node and a reference voltage node. The circuit also includes a replica transistor with a current path coupled between a supply voltage node and the input node. This replica transistor is coupled to operate as a diode, e.g. a MOSFET with its gate coupled to its drain. A current source can also be coupled in series with the current path of the replica transistor.
This embodiment sample and hold circuit also includes a bootstrap circuit, including a bootstrap capacitor. During a first phase, the bootstrap capacitor has a bias voltage (e.g., about 2 or 3 volts) placed across it. In a second phase, the bootstrap capacitor is placed in series with the replica transistor and coupled to the gate of the sampling transistor. In one example, this can be accomplished with a number of switches, e.g., transistors.
The preferred embodiment of the present invention is capable of high speed operation since it does not require an operational amplifier. This feature also minimizes the power consumption. As another advantage, in some aspects, the replica device is closed matched to the switching device. This feature helps to minimize distortion. Further, the preferred embodiment circuit does not have problems with drain induced barrier lowering (DIBL).


REFERENCES:
patent: 6020769 (2000-02-01), Vallancourt
p

Affiliated with

Also associated with

Rating

Low distortion sample and hold circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low distortion sample and hold circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low distortion sample and hold circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2597039