Low distortion FET oscillator with feedback loop for amplitude s

Details Low distortion FET oscillator with feedback loop for amplitude s Low distortion FET oscillator with feedback loop for amplitude s

1981-08-05

1984-06-12

Grimm, Siegfried H.

Oscillators

Solid state active element oscillator

Transistors

331117FE, H03B 512

Patent

active

044544855

ABSTRACT:
An FET oscillator includes means for controlling the gain of the oscillator to control its output level to thereby avoid limiting, and thus to reduce distortion of the oscillator output. A feedback loop is serially connected between the drain and gate electrodes to cause the gate direct voltage to increase negatively as drain output amplitude increases and thus reduce drain current and stabilize oscillator gain. The level of oscillation is adjustable by a potentiometer connection to the gate.

REFERENCES:
patent: 3416096 (1968-12-01), Kim
patent: 3513408 (1970-05-01), McGee
patent: 3534294 (1970-10-01), Auer
patent: 3624541 (1971-11-01), Lundstrom
patent: 4321563 (1982-03-01), Lesarte
Farell, "Designing FET Oscillators", EEE-Circuit Design Engineering, Jan. 67, pp. 86-90, 331-117 FE.
Brown, "MOS FET Stabilizes Oscillator's Output", Electronics, Feb. 3, 1969, p. 80, 331-117 FE.

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