Low distortion current switches for high speed current...

Details Low distortion current switches for high speed current... Low distortion current switches for high speed current...

2003-12-01

2004-12-21

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S136000

Reexamination Certificate

active

06833801

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to current steering digital to analog converters (DACs).
2. Prior Art
A thermometer-coded DAC consists of a large number of equal value current sources. These are each switched between the two DAC outputs using differential pairs, as shown in FIG.
1
. The differential pair transistors M
1
and M
2
are operated in saturation, and each have a voltage gain equal to G
SW
=g
m
/g
ds
when on. At any one time, one of these transistors is on, and the other is off.
There is a parasitic capacitance C
S
associated with the common source node of each differential pair. The potential on the common source node of the differential pair can be called V
CS
. The output of the DAC has a common mode voltage V
CM
and a differential voltage V
O
. When the voltage at the output of the transistor that is on changes by &Dgr;V
O
, the settled voltage at the common source node V
CS
is changed by a factor &Dgr;V
O
·g
ds
/g
m
. The current required to charge and discharge the capacitance C
S
is taken from the current source (signal current). It can be shown that this results in third order harmonic distortion for a differential output, as well as second order harmonic distortion for a single ended output. The amount of distortion is a function of output frequency, and the number of segmented bits, among other things.
The previously known methods available to minimize the distortion caused by the parasitic capacitance C
S
of the differential pair common source node may be summarized as follows:
1. The capacitance C
S
itself can be minimized. This is done by using switches that are as small as possible. The current source is typically implemented as a PMOS cascode current source. By locating the cascode transistor of the current source close to the switch common source node, the parasitic capacitance associated with routing between current source and switch can be minimized. Minimizing the width of the switch transistors M
1
and M
2
results in a high current density in these transistors, resulting in large gate voltage overdrive. This reduces the voltage drop available for the current sources, reducing the allowable gate voltage overdrive on the current sources. Thus, the sensitivity of the DAC currents to device mismatch is increased, resulting in degraded static linearity. Another way to optimize this is to build the DAC core from NMOS devices instead of PMOS devices. These typically have an advantage due to the higher electron mobility, allowing the designer to make the devices smaller by roughly a factor of 3.
2. The voltage gain of the switch transistors can be optimized. This voltage gain is limited by the g
m
/g
ds
of the switches. If the voltage gain is increased by increasing the channel length, the C
GS
also increases—hence not much can be gained in terms of distortion using only this method. Selecting a process with high g
m
/g
ds
—e.g. a BiCMOS process—using bipolar transistors as data switches, is one way to achieve this.
3. Regulating the cascode of the current source. This enhances the output impedance of the current source. Since the majority of the capacitance C
S
is associated with the switch transistors, this does not help third harmonic distortion much, but may be advantageous for static linearity and intermodulation distortion.
4. Bootstrapping the bulk of the switch and cascode transistors. This reduces C
S
roughly by a factor of 2 in a typical implementation. The amount of improvement is technology dependent.


REFERENCES:
patent: 5528186 (1996-06-01), Imamura
patent: 5548288 (1996-08-01), Lueng
patent: 5793231 (1998-08-01), Whittaker
patent: 6339391 (2002-01-01), Chung et al.
patent: 6525586 (2003-02-01), Ahmed et al.
patent: 6583744 (2003-06-01), Bright
patent: 6621432 (2003-09-01), Ganci
patent: 6664909 (2003-12-01), Hyde et al.
patent: 6703956 (2004-03-01), Mueller et al.
W. Schofield et al., “A 16b 400MS/s DAC with <-80dBc IMD to 300 MHz and <-160dBm/Hz Noise Power Spectral Density”, IEEE International Solid-State Circuits Conference, 2003, Session 7, DACs and AMPs, Paper 7.1.

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