Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls
Reexamination Certificate
1999-09-30
2001-05-22
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With intermittent comparison controls
C331S017000, C331S025000, C331S034000, C375S356000, C700S003000
Reexamination Certificate
active
06236277
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
BACKGROUND OF THE INVENTION
The present invention relates to industrial controllers for the real time control of industrial processes and in particular to a clock circuit that permits precise coordination of actions among different industrial controllers.
Industrial controllers are special purpose computers used for controlling industrial processes and manufacturing equipment. Under the direction of a stored program, the industrial controller examines a series of inputs reflecting the status of the controlled process and changes a series of outputs to control the industrial process. The inputs and outputs may be binary, that is on or off, or analog providing a value within a continuous range of values.
An industrial controller differs from a conventional computer in that the various components of the industrial controller may be separated by a considerable distance commensurate with the expanse of a large factory or manufacturing operation. The separated industrial controllers communicate via digital messages transmitted over one or more communication links.
These links necessarily introduce a delay in the communication between controllers depending on the distance between controllers and the amount of message traffic. In order to reduce this delay, time critical messages may be assigned a high priority on the link, where high priority messages obtain use of the shared communication media in preference to low priority messages. Normally, however, the proportion of the message carrying capacity of the communication link allocated to high priority messages is limited to ensure that low priority messages will also be ensured reliable transmission. As a result, a typical message between controllers will experience a significant and often unpredictable delay.
It is known to moderate the effects of this delay by providing each controller with an accurate clock to which control activities may be synchronized across the entire network of controllers. For example, a control event may be linked with a time of execution and transmitted in a control message to the various controllers before the time the control event must be performed. The actual execution of the control event is then triggered by the clock of each controller without concern about the time or receipt of the control message. Likewise, data being accepted by a given controller may be “time stamped” with the value of the controller's clock so that the data's precise time of arrival may be determined by another controller, even though the message transmitted to the other controller may be delayed.
For this approach to be successful, the clock used by a controller must be synchronized precisely with the clocks of the other controllers. This can be done by transmitting among all controllers a time synchronization signal. The signal may be transmitted with very high priority so as to the extent practical to cause each industrial controller to receive the synchronization signal at the same time so that it may update the value on its clock.
The time synchronization signal is transmitted only occasionally and the clocks allowed to run free between such update times so that transmission of the synchronization signal does not usurp the entire bandwidth of the communication link devoted to high priority signals.
U.S. Pat. No. 5,661,700 assigned to the assignee of the present invention and hereby incorporated by reference recognized that the periodic updating of a local clock of a controller can be disruptive if the clock has drifted sufficiently between updating times so that the process of the updating causes some time values to be skipped. An instruction intended to be executed at one of the skipped times value would in this case never be executed. Accordingly, the above patent teaches an updating process using two clocks, the first clock which is updated abruptly at the update time, and the second clock which is gradually adjusted during the interval between update times to reduce the error between itself and the first clock. Under this system no time values are skipped.
With increasing demands for high accuracy industrial control, the deviation of clocks that are allowed to free-run is no longer acceptable. Nevertheless, the alternative of providing more frequent update periods is undesirable because of the burden it places on the communication links.
BRIEF SUMMARY OF THE INVENTION
The present invention reduces the deviation of the local clocks between update times without increasing the frequency of the update times or the precision of the free running local clock. At the update time, an error is determined, but rather than applying the error to the local clock in the form of a single correction, the correction is broken into portions applied at regular intervals between update times. By breaking the correction process into portions, no time values are skipped and the maximum deviation of the clock between update times is significantly reduced.
In practice, the corrections are implemented by a controllable digital divider on the output of the oscillator that is switched between two divisors that on average correct the clock frequency to be obtained. The frequency of the switching between the divisors, each of which produces a single discrete clock frequency, allows an effective continuous range of frequency adjustment of the local clock.
Specifically then, the present invention provides a local clock for an industrial controller that is synchronizable to a remote master clock. The local clock includes an oscillator providing a set of discrete frequencies and a counter communicating with the oscillator to produce a first-time value. An input of the local clock periodically receives an error signal at a first rate, the error signal indicating the deviation of the first-time value from a second-time value of the master clock. A correction circuit responds to the error signal to switch the oscillator between two of the discrete frequencies at a second rate greater than the first rate so as to reduce the maximum deviation between the first time value and the second-time value.
Thus, it is one object of the invention to limit the maximum deviation between two free running clocks that are updated only at a first rate. Although the updating at the first rate limits the long term deviation of the clocks, the correction circuit by also updating at a second rate faster than the first rate, limits short term deviation of the clocks.
The oscillator may be a constant frequency time base providing an output to a divide-by-N digital counter also receiving a divisor input from the correction circuit. Change among the set of discrete frequencies is provided by changing the divisor.
Thus, it is another object of the invention to provide for a precise synchronization of two clocks in a digital system which provides only discrete frequency increments. The updating process provided by the correction circuit, which switches at a variable rate between two discrete frequencies, provides a nearly continuous range in average frequencies so that the master clock and local clock may be precisely coordinated.
The correction circuit may be an accumulator adding periodically at the second rate, an addend related to the error signal, the accumulator providing an overflow and underflow output communicating with the oscillator to switch the oscillator between the two discrete frequencies at the second rate determined by the rate of overflow and underflow.
Thus, it is another object of the invention to provide a simple mechanism for changing the rate of updating in proportion to the amount of error. Greater error signals provide greater rates of overflow or underflow in the accumulator.
The error signal may be a measure of frequency deviation between the oscillator of the local clock and the oscillator of the master clock, or a measure of time deviation between the first value of the local clock and the second value of the master clock, or a measure of
Grimm Siegfried H.
Horn John J.
Miller John M.
Rockwell Technologies LLC
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