Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-03-26
2003-06-24
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S347000, C257S510000, C438S424000
Reexamination Certificate
active
06583488
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device comprising trench isolation. The invention has particular applicability in manufacturing high density semiconductor devices with submicron design features and active regions isolated by shallow insulated trenches.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration (ULSI) require submicron features of significantly less than 0.25 microns, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon, bounding the active regions. This type of isolation has been referred to as local oxidation of silicon, or LOCOS.
In an effort to enable the further reduction of the size of semiconductor devices, semiconductor-on-insulator (SOI) wafers increasingly have been used in very-large scale integration (VLSI) or ULSI of semiconductor devices. An SOI wafer typically has a thin layer of silicon on top of a layer of an insulator material. In SOI technology, the semiconductor device is formed entirely in and on the thin layer of silicon, and is isolated from the lower portion of the wafer by the layer of insulator material. In an SOI integrated circuit, essentially complete device isolation may be achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. One advantage which SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
Another type of isolation structure is known as trench isolation, wherein shallow isolation trenches are etched in the substrate between the sites of semiconductor devices and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. STI has been widely applied to VLSI and ULSI semiconductor devices, and has been applied recently to SOI integrated. circuits for such devices.
Trench isolation has several limitations, which may be exacerbated in SOI devices. One problem is that sharp corners at the top of the trench can result in junction leakage currents. More specifically, such sharp corners may cause unwanted increases in the sub-threshold currents in the channel regions along the edge of the device areas when the FETs are switched on. The device threshold voltage can also be lowered. In order to avoid these problems, it has been found desirable to round the corners of such trenches to increase the radius of curvature and thereby decrease the electric field at the corners. This has been accomplished by, for example, oxidizing the entire inner surface of the newly formed trench, taking advantage of the fact that an exposed corner of a silicon layer oxidizes faster than a flat surface of the silicon layer, thus forming a rounded upper corner at the top of the trench.
However, with SOI devices, the corner rounding solution leads to a new problem. The problem in SOI devices arises as a result of the proximity of the dielectric insulation layer below the silicon active layer. In SOI devices, the shallow isolation trench is etched through the silicon layer to the insulation layer. When the exposed portion of the silicon on the sidewalls of the newly formed trench is oxidized during the process of rounding the corners, a wedge or “bird's beak” of new oxide may form on the underside of the silicon active layer adjacent the isolation trench, between the silicon active layer and the underlying layer of insulating material of the SOI wafer. Thus, as the oxide grows on the sidewalls of the trench, it may grow laterally between the lower edge of the silicon active layer and the underlying oxide insulation layer. In essence, during the process of oxidation which is intended to round the upper corner of the silicon active layer, the lower corner of the silicon active layer is also rounded, forming the “bird's beak” between the silicon active layer and the underlying oxide insulation layer. The problem results when, during subsequent high temperature processing steps after the trench has been filled with a trench fill material, thermal expansion of the trench fill material and of the “bird's beak” creates defects in the silicon crystal structure and/or lifts the silicon layer, due to the pressure of the differently expanding trench fill material in particular, and to some degree, due to expansion of the oxide of the bird's beak. The resulting defects in the crystal structure of the active region may change the electrical characteristics of the semiconductor. The lifting of the silicon layer distorts the surface of the semiconductor device from its desired planarity to an undesirable non-planar condition. As semiconductor device dimensions continue to become smaller, problems such as these both occur more easily and become less tolerable.
Thus, there exists a need for STI methodology applicable to SOI semiconductor devices wherein the problems resulting from sharp corners can be alleviated without the problems resulting from “bird's beak” on the underside of the silicon active layer adjacent the isolation trench.
SUMMARY OF THE INVENTION
The present invention provides a method of avoiding problems commonly associated with formation of the “bird's beak” while providing rounded upper corners on the silicon active layer in shallow trench isolation of SOI semiconductor devices.
In one embodiment, the present invention relates to a method of isolation of active regions on a silicon-on-insulator semiconductor device, comprising the steps of:
providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate;
etching through the silicon active layer to form an isolation trench, the isolation trench defining an active region in the silicon active layer;
forming a liner oxide by oxidation of exposed silicon in the isolation trench; and
filling the isolation trench with a tensile stress-reducing low density trench isolation material, without thereafter densifying the low density trench isolation material.
In one embodiment, the method further comprises rounding at least one square upper corner of the silicon active layer.
In one embodiment, the step of forming the liner oxide occurs simultaneously with the step of rounding at least one square upper corner. In one embodiment, the step of forming a liner oxide results in formation of a bird's beak. In one embodiment, the step of forming a liner oxide occurs substantially simultaneously with the step of rounding at least one corner of the silicon active layer. In one embodiment, the tensile stress-reducing low density trench isolation material comprises a plurality of dielectric spacers. In one embodiment, the plurality of dielectric spacers comprise a dielectric gas. In one embodiment, the tensile stress-reducing low density trench isolation material has a dielectric constant in the range from about 1.05 to about 3.5.
In another embodiment, the present invention relates to a method of making a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolat
Advanced Micro Devices , Inc.
Elms Richard
Renner , Otto, Boisselle & Sklar, LLP
Wilson Christian D.
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