Low delay or low loss switch for ATM

Details Low delay or low loss switch for ATM Low delay or low loss switch for ATM

1993-09-23

1995-02-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 856, 370 61, H04L 1256

Patent

active

053901762

ABSTRACT:
An ATM switching arrangement in which two types of cells are distinguished. A first type of cells is marked as low loss cells and a second type of cells is marked as low delay cells. In the switching arrangement a cell buffer (9) is subdivided into a first memory area (LL) for the low loss cells and a second area (LD) for the low delay cells. In the case of the cell buffer (9) being completely filled, low loss cells get read-in priority over low delay cells. In reading out from the cell buffer low delay cells take priority over low loss cells, unless the low delay area is empty. It is also possible to set a threshold value for the content of the low loss area; when the content of the low loss area exceeds the threshold value outputting of the low loss cells can then be started.

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T. Koinuma et al., "An ATM Switching System Based on a Distributed Control Architecture", Int. Switching Symposium 90, vol. 50, May 1990, pp. 21-26.
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CCITT Recommendation I.361-1991.

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