Low delay ATM switching system using idle cells stamped with ref

Multiplex communications – Wide area network – Packet switching

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H04Q 1104

Patent

active

053373081

ABSTRACT:
In a multi-stage switching system, a time stamp is attached to each cell at an entry point of the system indicating the time of arrival of the cell, and the cell is transferred to a network comprising multiple switching stages each being composed of basic switching modules. The switching modules of all stages are interconnected to form the network. Each switching module comprises a self-routing switch and buffers connected thereto. The time stamp of cells arriving at a given one of the switching modules, where the cells are likely to arrive out of sequence, is constantly monitored and a minimum value of the time stamps is detected. When an empty buffer exists in the given switching module, an idle cell containing the time stamp of the minimum value is generated at the output of the empty buffer.

REFERENCES:
patent: 4661947 (1987-04-01), Lea et al.
patent: 4858232 (1989-08-01), Diaz et al.
patent: 4894823 (1990-01-01), Adelmann et al.
patent: 5086428 (1992-02-01), Perlman et al.
H. Obara, "Design of a Multi-Stage Self-Routing Switch with a Distributed Cell Sequence Control", Institute of Electronics, Information & Communications Engineers of Japan, J72-B-1, No. 9, pp. 698-709.

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