Low delay and low loss packet switch

Details Low delay and low loss packet switch Low delay and low loss packet switch

2006-03-07

2006-03-07

Sam, Phirin (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395420

Reexamination Certificate

active

07009975

ABSTRACT:
In a telecommunication switching arrangement where data packets have multi-level indices associated with the loss and delay aspects of the data packet, a mathematical operation on the indices allows the switching arrangement to assign data packets to groups. The sequence in which the data packets are transmitted by the switching arrangement is based on the group to which the data packet belongs. This effectively results in a relative prioritization of the data packets. Additionally, the loss and delay indices determine storage priority and relative priority inside a group. The switching arrangement achieves low loss and low delay for the data packets to be transmitted.

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patent: 6341313 (2002-01-01), Kanoh
patent: 6563826 (2003-05-01), Shikama
By Chao H.J. et al. “An ATM Queue Manager Handling Multiple Delay and Loss Priorities”, IEEE / ACM Transactions on Networking vol. 3, No. 6, Dec. 1, 1995, pp. 652-659.

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