Low defect method for die singulation and for structural...

Semiconductor device manufacturing: process – Semiconductor substrate dicing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S461000, C438S462000, C438S463000, C438S464000

Reexamination Certificate

active

06573156

ABSTRACT:

BACKGROUND
Microelectromechanical systems (MEMS), which are made up of several micromachined electrical-mechanical structures, have a size typically on a millimeter scale or smaller. These micromachined structures are used to produce MEMS devices that are used in a wide variety of applications including, for example, sensing, electrical and optical switching, and micromachinery (such as robotics and motors). MEMS devices utilize both the mechanical and electrical attributes of a material to achieve desired results. Because of their small size, MEMS devices may be fabricated using semiconductor processing methods and other microfabrication techniques, such as thin-film processing and photolithography.
In a typical MEMS process, MEMS devices are fabricated by thin film processes on a wafer. The wafer is then diced to separate the MEMS devices from each other such as by sawing, scoring, cutting, grinding, or other similar separation technique. A drawback of traditional dicing tools is that they can damage the devices. This is particularly true when MEMS devices are involved. MEMS devices sometimes can contain delicate structures that are sensitive to shock, vibration, and jarring.
Moreover, debris contamination often caused by traditional mechanical dicing tools is of particular concern in MEMS applications. This is because debris can become lodged between structures, inhibiting movement of and/or causing shorting between the structures, thus rendering the MEMS device inoperable. In some MEMS applications, several tens to several hundreds or more of MEMS devices may be on a single chip. Malfunction of a single device can cause the entire chip to be unusable.
In addition, traditional separation techniques can be time consuming, constraining manufacturing throughout. This is particularly true in very large chip arrays of hundreds, to thousands, or more.
Futhermore, in practicality, traditional dicing techniques limit separation of the chips into square or rectangular shaped chips. This limitation is something that may not be advantageous in all MEMS applications.
What is needed is an improved method for chip separation that provides improved yields and device reliability. Moreover, what is needed is an improved method for separation of MEMS chips having delicate structures. In Addition, what is needed is a less time consuming method for chip singulation. Further, what is needed is an improved method, allowing cost effective, high yield separation of non-traditional shaped chips.
SUMMARY
In certain implementations, a method for chip singulation is provided including etching a frontside dicing trench from a front side of a wafer, forming a temporary holding material in the frontside dicing trench, etching a backside dicing trench from a back side of the wafer along the frontside dicing trench, removing the temporary holding material and releasing the chip from the wafer and/or an adjacent chip.
In some implementations, the method includes etching through surface deposited layers on the front side of the wafer. The method may further include completely filling the frontside dicing trench with the temporary holding material and etching the backside dicing trench to the temporary holding material that is in the frontside dicing trench, such that removing the temporary holding material self-dices the wafer.
In certain implementations, the method includes surrounding MEMS structures with the temporary holding material so as to hold the structures during etching of the back side of the wafer. This method may include providing a carrier wafer over the front side of the wafer.
In certain implementations, the temporary holding material may be parylene, deposited by vapor deposition. In such implementations, the parylene may be removed by dry etching, such as by an oxide plasma etch.


REFERENCES:
patent: 5904546 (1999-05-01), Wood et al.
patent: 6048777 (2000-04-01), Choudhury et al.
patent: 6107164 (2000-08-01), Ohuchi et al.
patent: 6117347 (2000-09-01), Ishida
patent: 6200882 (2001-04-01), Drake et al.
patent: 6277666 (2001-08-01), Hays et al.
patent: 0182218 (1986-05-01), None
patent: 0182218 (1991-06-01), None
patent: 00499752A (1992-08-01), None
patent: 0551616 (1992-12-01), None
patent: 0551616 (1992-12-01), None
patent: 00550014A (1993-07-01), None
patent: 00603514A (1994-06-01), None
patent: 01026725A (2000-08-01), None
patent: 01093169A (2001-04-01), None
patent: 01130629A (2001-09-01), None
patent: WO 01/56063 (2001-08-01), None
Schindling, English Abstract, Patent No. 00551616 EP B1, patent application No. 92121062, Dated Filed Dec. 10, 1996.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Low defect method for die singulation and for structural... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low defect method for die singulation and for structural..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low defect method for die singulation and for structural... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3112105

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.