Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1998-07-10
2002-02-12
Chin, Stephen (Department: 2734)
Pulse or digital communications
Receivers
Angle modulation
C375S340000, C341S088000, C341S108000, C341S110000, C341S123000, C341S126000
Reexamination Certificate
active
06347123
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to multi-rate digital signal processing systems. Specifically, the present invention relates systems for effecting sample rate conversion of a digital signal.
2. Description of the Related Art
Telecommunications systems that transmit and receive different types of signals such as facsimile, speech and video signals must often process various signals at different rates commensurate with the bandwidths of the corresponding signals. The process of converting a signal from a given rate to a different rate is called sample rate conversion. Systems that employ multiple sampling rates in the processing of digital signals are called multi-rate digital signal processing systems.
Multi-rate systems typically employ one of two general methods to effect sample rate conversion. One method involves passing the digital signal through a digital-to-analog converter (DAC) and then re-sampling the resulting analog signal at the desired rate via an analog-to-digital converter (ADC). However, this method often results in undesirable signal distortion introduced by the DAC during signal reconstruction and by quantization effects during analog-to-digital conversion.
These problems are typically avoided by a second method that involves performing the sample rate conversion entirely in the digital domain via a digital sample rate converter. One type of digital sample rate converter is a direct-form finite impulse response (FIR) filter. The filter adjusts an input sample rate F
s
by a factor of I/D and includes an up-sampler connected in series to a lowpass filter, the output of which is connected to a down-sampler. The up-sampler interpolates, i.e., up-converts the input sample rate by a factor I. The low-pass filter removes resulting undesirable spectral images and the down-sampler decimates, i.e., down-converts, the resulting interpolated signal by a factor D. The up-sampling performed by the up-sampler introduces I-1 zeros between successive samples of the input signal. If I is large, most of the signal components in the FIR filter are zero. Consequently, most of the filter computations including multiplications and additions result in zeros, representing wasted power. Furthermore, while the filter performs computations on all samples, only one out of every D output samples is required at the output of the filter. This represents additional filter inefficiency.
More efficient FIR sample rate converters are known, however, sample rate conversion is still typically realized by inserting I-1 zeros between input samples and then filtering the resulting sequence. In addition, the filter computations are performed at the high sampling rate of I*F
s
, where F
s
is the sample rate of the signal input to the FIR sample rate converter. The high sampling rate results in large power consumption.
A second type of digital sample rate converter is implemented via polyphase filters. The polyphase filter computations are performed at the relatively low sampling rate of F
s
. However, polyphase sample rate converters designed to adjust the input sample rate F
s
by a factor of I/D require a bank of at least I polyphase filters. The requirement often results in computationally inefficient, space inefficient, and energy inefficient sample rate converters. These disadvantages are particularly problematic in applications such as cellular telephones used in digital telecommunications systems where size and power consumption are of paramount importance.
Cellular telecommunications systems are characterized by a plurality of mobile transceivers in communication with one or more base stations. Each transceiver includes a transmitter and a receiver. In a typical transceiver, an analog radio frequency (RF) input signal, received by an antenna, is downconverted by an RF section to an intermediate frequency (IF). Signal processing circuits perform noise filtering and adjust the magnitude of the signal via analog automatic gain control (AGC) circuitry. An IF section then mixes the signal down to baseband and converts the analog signal to a digital signal. The digital signal is then input to a baseband processor for further signal processing to output voice or data.
Similarly, the transmitter receives a digital input from the baseband processor and converts the input to an analog signal. This signal is then filtered and upconverted by an IF stage to an intermediate frequency. The gain of the transmit signal is adjusted and the IF signal is upconverted to RF in preparation for radio transmission.
In both the transmit and receive sections, signal gain adjustment and mixing is typically performed in the analog domain. This necessitates the use of a plurality of local oscillators (LOs) and low-pass filters for signal downconversion, upconversion, and mixing. Analog local oscillators tend to be bulky and require the use of one or more phase-locked loops. As is well known in the art, phase-locked loops are large, expensive circuits that consume a considerable amount of power. In addition, the requisite analog gain circuits and mixers are especially prone to undesirable gain and phase mismatch and the analog low-pass filters are expensive to implement.
Hence, a need exists in the art for a computationally-efficient, power-efficient and space-efficient sample rate converter. There is a further need for an efficient transceiver that maximizes the benefits of the efficient sample rate converter and eliminates the need for analog baseband-to IF-mixers and gain control circuits.
SUMMARY OF THE INVENTION
The need in the art is addressed by the low power sample rate converter of the present invention. In the illustrative embodiment, the inventive sample rate converter is adapted for use with a telecommunications system transceiver and includes a first circuit for providing an input signal characterized by a first sample rate. The first circuit also provides a delayed version of the input signal. A second circuit periodically multiplies, at a second sample rate, a first sample in the input signal by a first predetermined coefficient in accordance with a predetermined transfer function and provides a first signal in response thereto. A third circuit periodically multiplies, at the second sample rate, a second sample in the delayed version of the input signal by a second predetermined coefficient in accordance with the predetermined transfer function and provides a second signal in response thereto. A fourth circuit combines the first signal and second signal and provides a rate-converted version of the input signal as an output signal in response thereto.
In a specific embodiment, the delayed version of the input signal is delayed by one sample with respect to the input signal. The sample rate converter further includes a counter. The counter is clocked by a first periodic signal having a first frequency related to the first sample rate by a predetermined fraction. The counter is cleared by a second periodic signal having a second frequency equivalent to the first sample rate. The counter produces a counter output at the first frequency. In the preferred embodiment, the predetermined fraction is ⅓ and the first predetermined coefficient is equivalent to the sum of 1 and the counter output. The second predetermined coefficient is equivalent to the difference of 2 and the counter output.
The fourth circuit includes an adder for adding the first signal and the second signal and providing the output signal in response thereto. In an exemplary embodiment, the predetermined transfer function is:
(1+z
−1
+z
−2
)
2
The predetermined transfer function is represented by the following coefficient sequence: [1 2 3 2 1].
The sample rate converter includes a clock that generates a first clock signal. An input circuit receives the input signal. An enable circuit compares the first clock signal to the input signal and provides an enable signal when the input signal is stable near an edge of a clock pulse in the first clock signal. The counter recei
Macek Daniel T.
Mathe Lennart
Brown Charles D.
Chin Stephen
Edwards Christopher
Ha Dac V.
Qualcomm Incorporated
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