Low current, fast, CMOS static pullup circuit for static random-

Details Low current, fast, CMOS static pullup circuit for static random- Low current, fast, CMOS static pullup circuit for static random-

1992-06-19

1993-11-23

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 36518909, 36518911, H03K 19017

Patent

active

052647412

ABSTRACT:
A pullup circuit for use with plurality of N-Channel pulldown transistors connected to a bit line includes a P-channel MOS pullup transistor connected between the bit line and a voltage rail. An inverter is connected between the bit line and the drain of an N-Channel MOS transistor having its gate connected to the voltage rail and its source connected to the gate of the P-Channel MOS pullup transistor. A first P-Channel MOS transistor is connected between the voltage rail and the gate of the P-Channel MOS pullup transistor. A second P-Channel MOS transistor having its gate connected to ground is connected between the bit line and the gate of the first P-Channel MOS transistor. Four P-Channel MOS divider transistors are connected between the drain of the first P-Channel MOS transistor and ground. The gates of the P-Channel MOS divider transistors are connected together to ground. The P-Channel MOS pullup transistor and the N-Channel MOS pulldown transistors are large. The first and second P-Channel MOS transistors, the first N-Channel MOS transistor, and the P-Channel MOS divider transistors are close to minimum size. The P-Channel and N-Channel devices comprising the inverter devices are larger than minimum size.

REFERENCES:
patent: 4750155 (1988-06-01), Hsieh
patent: 4771284 (1988-09-01), Masleid et al.
patent: 4918341 (1990-04-01), Galbraith et al.
patent: 5020028 (1991-05-01), Wanlass
patent: 5041746 (1991-08-01), Webster et al.
patent: 5056062 (1991-10-01), Kuwabara et al.
patent: 5109167 (1992-04-01), Montegani
patent: 5148390 (1992-09-01), Hsieh
patent: 5191555 (1993-03-01), Tabacco et al.

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