Low crosstalk type switching matrix of monolithic semiconductor

Details Low crosstalk type switching matrix of monolithic semiconductor Low crosstalk type switching matrix of monolithic semiconductor

1978-03-06

1981-01-20

Munson, Gene M.

357 35, 357 38, 357 39, 357 89, H01L 2704, B01L 2974, H01L 29747, H01L 2972, H01L 2972

Patent

active

042465940

ABSTRACT:
The switching matrix with a plurality of individual lateral type PNPN type switching elements is disposed on a one chip silicon. The chip includes a double layered substrate having a thin P type layer with low impurity concentration epitaxial-grown on a P.sup.+ type layer with high impurity concentration and an N type layer with low impurity concentration epitaxially grown on the P type layer. The substrate has a low resistance. An N.sup.+ type buried layer with high impurity concentration is diffused into the junction between the P type layer and the N type layer at the location where the switching element is to be disposed. The switching element is formed in the N type layer right above the N.sup.+ type buried layer. P.sup.+ type isolation region with high impurity concentration is diffused into the N type layer, not contacting the N.sup.+ type buried layer but the substrate P type layer and enclosing the N type gate region of the switching element. At this time, between adjacent P.sup.+ type isolation regions is formed a high resistive separation region of the N type layer. With such a construction, the low resistive P/P.sup.+ type double layered substrate and the high resistive N separation layer cooperate to remarkably reduce the signal crosstalk between switching elements.

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