Low cost writethrough cache coherency apparatus and method for c

Details Low cost writethrough cache coherency apparatus and method for c Low cost writethrough cache coherency apparatus and method for c

1996-06-13

1998-06-16

Robertson, David L.

Electric lamp and discharge devices: systems

Pulsating or a.c. supply

Plural load device systems

315462, G06F 1200

Patent

active

057685576

ABSTRACT:
A method for supporting a writethrough cache in a computer system not otherwise supporting cache is disclosed. Cache coherency is guaranteed by a cache coherency module detecting the CPU programming a DMA controller to allow a device other than the CPU to transfer data to main memory and, until the data transfer is concluded, flushing the cache each time the CPU reads an address other than an address of a standard computer system component. The cache is also flushed upon conclusion of the data transfer. In computer systems including a bus master device, the cache is flushed whenever the cache coherency module detects the CPU reading an address other than an address of a standard computer system component and whenever the cache coherency module detects an interrupt other than a standard computer system interrupt. Also disclosed a method to automatically determine the range of cacheable addresses in the computer system and to turn on the cache after the computer system is reset.

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