Education and demonstration – Means for demonstrating apparatus – product – or surface... – Chalkboard or equivalent means having easily erasable surface
Reexamination Certificate
1999-06-07
2001-08-07
Bowers, Charles (Department: 2813)
Education and demonstration
Means for demonstrating apparatus, product, or surface...
Chalkboard or equivalent means having easily erasable surface
C438S427000
Reexamination Certificate
active
06270353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a process to form planarized shallow trench isolation structures using a non-conformal high density plasma (HDP) oxide deposition.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region foxned from a trench fill dielectric layer formed within the trench. Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar trench isolation regions and active semiconductor regions the limited depth of focus typically achievable with advanced photo exposure.
Two major challenges in achieving the shallow trench isolation (STI) structure are: (1) filling the narrow trenches without voids or seams defect, and (2) planarization of trenches of diverse widths. Conventional STI processes may employ conformal low pressure chemical vapor deposition (LPCVD) TEOS deposition and a complicated planarization process which uses two step photo-resist coating, reactive ion etch (RIE) etch back and chemical mechanical polish (CMP). Due to the nature of conformal LPCVD TEOS deposition, seams are generally present in the LPCVD TEOS filled shallow trench isolation region. The seams become a major problem as the device dimensions scale downward and the aspect ratio of the STI increases.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional methods, it is, therefore, an object of the present invention to provide a method for planarizing a structure on a semiconductor substrate. The method may include providing the semiconductor substrate having raised and lowered regions with substantially vertical and horizontal surfaces. The vertical surfaces may have a predetermined height. Further, the method may include depositing filler material over the horizontal surfaces to at least a thickness equal to the predetermined height so as to provide raised and lowered regions of the filler material. The method may also include selectively removing the raised regions of the filler material.
The filler material may be non-conformal high density plasma (HDP) oxide. Additionally, the lowered regions of filler material may be covered with a mask and the filler material on the raised regions may be etched. The raised regions may not be protected by the mask.
An oxide pad and a nitride pad may be provided on the semiconductor substrate. The raised and lowered regions may be formed by masking regions of the nitride pad and etching exposed areas of the nitride pad. The oxide pad and the nitride pad may be further removed after selectively removing the raised regions of the filler material. Further, only the raised regions of the filler material are etched without etching the lowered regions of the filler material.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.
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Anonymous, “Sensitive Surface Damage Avoidance During Polishing”, Research Disclosure, Kenneth Mason Publications Limited, Nov. 1991, No. 331.
Pye et al., “High-density plasma CVD and CMP for 0.25-um intermetal dielectric processing” Solid State Technology, Dec. 1995, pp. 65-72.
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Andrews John W.
Hwang Bao T.
Landis Howard S.
Mei Shaw-Ning
Tyler James M.
Blum David S
Bowers Charles
International Business Machines - Corporation
McGinn & Gibb PLLC
Walter, Jr. Howard J.
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