Low cost memory tester with high throughput

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C324S765010

Reexamination Certificate

active

06204679

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the manufacture of semiconductor components and more specifically to testing of semiconductor components during manufacture.
BACKGROUND OF THE INVENTION
Semiconductor components are tested during the manufacturing process to identify and sort out non-functioning parts. Testing also allows semiconductor components to be sorted based on the performance actually achieved by each part.
In manufacturing semiconductor components, throughput of the manufacturing process is very important. Large capital investment is required to build a manufacturing plant. For such a venture to be profitable, many semiconductor chips must be made at the plant. It is generally desired that the testing operation run with the same throughput as the rest of the manufacturing process.
Testing is usually performed with automated test equipment, such as the J990 family of test systems sold by Teradyne, Inc. The automated test system, or “tester”, typically has a main frame and a test head. The test head contains electronic circuitry that generates test signals that are applied to a device under test or compares signals produced by the device under test to expected values. Data for the circuitry in the test head is generally provided from a main frame portion of the tester. The main frame typically contains a pattern generator that sends signals to the test head circuitry specifying the signals to apply to the device under test or that are expected from the device under test. In addition, the main frame includes power supplies and other support circuitry needed by the test system.
The test head contains circuitry to generate and measure test signals for at least one device being tested. The collection of signals that are connected to one device under test is called a “site.” To increase throughput, a test head will often contain several sites.
The circuitry that generates and measures test signals for one lead of a device being tested is called “pin electronics.” Several copies of the pin electronics, to provide test signals for several leads, are fabricated on one printed circuit board, called a pin electronics card. The test head is generally made up of a card cage in which pin electronics cards are mounted. Adding more pin electronics cards into the test head can increase the number of sites on the test head.
The electrical circuitry inside the test head that generates the signals for one site is connected to a contactor, which makes electrical contact to the leads of the semiconductor device under test.
The test head interfaces to a “handler”. The handler presses semiconductor chips into the contactors and removes them after the test. Based on the results of the tests, the handler might also sort the chips by performance grades.
In addition to physically moving the semiconductor chips to the required positions where each chip can make contact with a test site, the handler thermally conditions the chips. Testing is often performed at two or three different temperatures to verify that the chips operate over a range of environmental conditions. One test is usually performed at ambient temperature. Another test is usually performed at an elevated temperature between 105° C. and 165° C. Often, a test is performed at a cold temperature, between 0° C. and −65° C. Usually, the test at ambient temperature is a full functional test of the device under test, meaning that all functions of the chip are tested. The tests at elevated and cold temperature will often not be full functional tests so that the testing process can be faster. The faster tests verify that some subset of the functions of the device still operate at the higher or lower temperature.
Two different strategies have been used for testing parts at multiple temperatures.
FIG. 1A
shows several test systems, such as
110
A and
110
B, each operated at different temperatures. Each test system
110
includes a main frame
112
connected to a test head
114
. Test head
114
docks to a handler
116
. Material handling units, such as
120
A,
120
B and
120
C load and unload semiconductor devices at the handlers
116
.
FIG. 1A
shows trays
118
used to carry semiconductor components under test. In some instances, the devices under test are carried in tubes or other types of carriers. Inside the handlers
116
, the devices under test are queued up in a temperature controlled chamber. Inside this chamber, the parts are brought to the required test temperature before they are plugged into the sockets that connect them to the test head
114
. Once the devices are tested at one temperature at test system
110
A, a material-handling unit
120
B moves the trays
118
to test system
110
B for testing at a different temperature.
Material handling units
120
A . . . C are shown schematically as wheeled carts. The carts can, for example, be robotic carts, though the semiconductor components can be moved by a person. In addition to a wheeled cart, the material handling system must include elements to move the semiconductor components from the cart to the handler and to perform other device handling operations. The equipment to perform these processes is not expressly shown because it is well known in the art.
An alternative test strategy is shown in FIG.
1
B. Test system
150
includes a main frame unit
152
and a test head
154
. Distribution unit
162
routes test signals to individual test sites within the thermal chamber
156
. In comparison to system
110
A and
110
B in
FIG. 1A
, test system
150
includes a much larger thermal chamber
156
. More devices are loaded into the thermal chamber
156
at one time. To test at different temperatures, the thermal chamber
156
is loaded with devices. The thermal chamber is then brought to the required temperature, but testing does not begin until the parts have come to thermal equilibrium at the desired temperature.
Distribution unit
162
routes test signals to the parts inside the thermal chamber. In this way, there is not one set of pin electronics for each device in the thermal chamber. Rather, once the devices are brought to thermal equilibrium, devices are tested sequentially.
A test system for functional test of semiconductor memories typically has 16 or fewer sites. Though some test systems have 32 or 64 sites for functional test. Such testers are generally used in a system configured as in FIG.
1
A. Some testers, called “burn-in testers”, have been made with many sites, such as on the order of one thousand test sites. Such testers are more likely to resemble the system illustrated in FIG.
1
B.
A “burn-in tester” usually performs a burn-in test during which the devices under test are thermally stressed by being kept at either an elevated or a low temperature for an extended period of time. During the burn-in test, measurements are made to determine whether the operation of the semiconductor device has gone outside of specifications. Once the tests at one temperature have been completed, the temperature within the thermal chamber is changed and testing is repeated at a different temperature. A full burn-in test cycle can literally take hours and the approximately 10 minutes it takes to change the temperature inside the burn-in oven is a small fraction of this time.
One disadvantage of the approach of
FIG. 1A
is that multiple test systems require substantial floor space in the factory making semiconductor devices. Because of the high cost of making a semiconductor fabrication facility, there is a high cost associated with each square foot of floor space occupied by test equipment. Also, there are inefficiencies each time the parts are loaded or unloaded from a test system.
FIG. 1B
also suffers from disadvantages. While the floor space occupied by the test system is much smaller, the test time is longer because there is a wait while the parts are brought to the required temperature. For burn-in tests that take hours, this short wait is not significant. However, a delay in testing a part while the temperature changes could be significant per

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Low cost memory tester with high throughput does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low cost memory tester with high throughput, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low cost memory tester with high throughput will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2485409

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.