Low cost emulation scheme implemented via clock control using JT

Details Low cost emulation scheme implemented via clock control using JT Low cost emulation scheme implemented via clock control using JT

1996-11-15

1998-09-22

Beausoliel, Jr., Robert W.

Excavating

371 2236, G01R 3128

Patent

active

058125620

ABSTRACT:
An integrated circuit includes a test port operating at a first clock speed and at least one functional logic block operating at a second clock speed which is faster than the first clock speed. A control register, formed by boundary scan cells, operates at the first clock speed and provides control inputs to the functional block to control emulation tasks. The control register is writable via a serial shift operation through the test port while the functional block is operating. The outputs of the control register which are being provided to the functional block are held constant during the serial shift operation. An observation register, formed by boundary scan cells, operates at the first clock speed, and is readable through the test port via a serial shift operation, while the functional block is operating. The observation register receives signals from the functional block indicating status of the functional block.

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