Low cost dielectric isolation method for integration of...

Details Low cost dielectric isolation method for integration of... Low cost dielectric isolation method for integration of...

2006-05-23

2006-05-23

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S093000, C257S374000, C257S564000, C257S397000, C257S501000, C257S506000, C438S353000, C438S219000, C438S294000

Reexamination Certificate

active

07049677

ABSTRACT:
A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.

REFERENCES:
patent: 5369309 (1994-11-01), Bacrania et al.
patent: 6225664 (2001-05-01), Endo et al.
patent: 6269011 (2001-07-01), Ohshima

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