Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
1995-08-01
2002-10-22
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010, C324S763010
Reexamination Certificate
active
06469493
ABSTRACT:
This invention relates generally to automatic test equipment and more specifically to low cost automatic test equipment for semiconductor devices.
Semiconductor devices, such as memory chips and micro controllers, are usually tested at least once during their manufacture. Testing is conventionally performed with automated equipment called a “tester.” A tester is a computer controlled device with many input/output points. Each of the input/output points is connected to one lead of the semiconductor device through a device called a prober or a handler.
So that one tester can be used to test many different types of semiconductor devices, the tester can be programmed to generate “patterns.” The pattern defines what stimuli are applied to the device under test and the expected responses to that stimuli. Defective devices are detected because they do not produce the expected responses.
To make a tester which is the most useful, it is desired that the tester be able to apply or check for any value at any time at any pin of the device being tested. Typically, a pattern is made up of a string of vectors. Each vector contains information about the values to be applied to or expected to be detected at each pin of the device under test during one period of the tester's operation. This information includes the data value, timing information and format information.
Format information indicates at a minimum whether the data is a value which should be driven or is a value expected to be observed at the pin. In some testers, format information also indicates the format which a valid logic 1 or 0 should take. Examples of formats are return-to-zero, nonreturn-to-zero and surround by complement.
Most testers allow the length of a period to be programmed. The period is generally the same for signals applied to all pins in the tester. The timing information is programmed as a delay relative to the start of the period.
To provide the required flexibility, a typical tester has an architecture with some centralized control, or “global,” control circuitry. In addition, there are multiple identical circuits called “channel electronics” or more simply “channels.” Each channel provides the signals for one pin of the device under test.
FIG. 1
shows a typical prior art tester
100
. A test pattern is stored in memory
120
. For each cycle of tester operation, test system control
110
reads one vector from memory
120
. Then, the data, format and timing information are provided to a plurality of channels
114
. In addition, test system control
110
provides a timing signal to each of the channels which defines a reference time from which all delays are calculated. This is sometimes called the “beginning of period” signal or “period clock”.
Each channel
114
contains several timing generators
114
. Each timing generator produces a timing signal, sometimes called an “edge,” a programmed time after the beginning of period signal. There are multiple timing generators
116
because each is dedicated to perform a specific function. For example, one timing generator is dedicated to turning on the drive voltage and one is dedicated to turning off the drive voltage. Another is dedicated to starting a comparison operation while another to stopping the comparison operation.
The edges from all of the timing generators
116
are passed to formatter
118
. Formatters
118
contain the drivers and comparators which actually provide or measure the data. The time when each operates is controlled by the edge signals. In this way, signals are driven to or measured at the device under test
112
.
For a tester which can test even a modestly complicated part, there will be more than fifty and likely more than one hundred channels
114
. The channel circuitry, thus, accounts for a large portion of the cost of tester
100
. The cost can be particularly high because low cost technologies, such as CMOS, are not suitable for the channel circuitry in many testers. Rather, ECL components are widely used because they can operate at high clock rates and are very stable.
CMOS circuitry made using widely available 0.8 micron processes has a maximum operating frequency of approximately 100 MHz. Components made with state of the art 0.3 micron processes can extend the operating frequency to as much as 200 MHz. This means that the clock likely has a resolution of only 10 nsec, and in the best case a resolution of 5 nsec. When CMOS digital signals are synchronized relative to the clock, they have a resolution of only 5 to 10 nsec. Often, a resolution less than 250 psec resolution is required for a tester. Further, programmed values should be very accurate.
To provide finer resolution, the delay is broken into two pieces: the integer number of clock periods plus some fractional portion of a clock signal. A counter produces an output pulse after the required integer number of clock periods. The fractional part of the delay is provided by delaying this pulse in either a programmable delay line or analog circuitry called a timing “interpolator” or “vernier.” Timing generation circuitry of this type is described in U.S. Pat. No. 4,231,104 to St. Clair and U.S. Pat. No. 5,274,796 to Conner.
The difficulty with using CMOS for such an arrangement is that the delay of CMOS circuits varies as a function of temperature of the devices. The delay of a CMOS circuit changes approximately 0.3%/° C. to 0.4%/° C. Such a large change as a function temperature means that the same delay programmed into a channel will produce different results when operated at different temperatures. In addition, CMOS components have large part-to-part variations. Delays through parts which have been identically processed can vary by as much as 20 or 30%.
One simple approach is to calibrate the tester each time the operating temperature changes significantly. Many calibration techniques are known. U.S. Pat. No. 4,724,378 to Murray et al. describes an external calibration device used to compute timing correction values which are stored in the tester memory. Other techniques are known for deriving the calibration values, including the addition of circuitry to the tester to derive the calibration values. However, the process of calibrating the tester can be very time consuming.
Mechanical solutions to keep the CMOS chips at uniform temperatures are possible. However, requiring cooling components is expensive and defeats the purpose of using CMOS to provide a low cost tester. It also does not eliminate the delay differences caused by part-to-part variations.
An alternative way to compensate for differential delays is to heat the CMOS chips. U.S. Pat. No. 4,980,586 to Sullivan et al, uses circuitry on the chip to heat the CMOS chip to the desired operating temperature. In addition, that patent describes a feed back mechanism in which a ring oscillator on the chip is used as part of circuit to measure actual delays. The frequency of the signal in the ring oscillator is inversely proportional to the delay. A control signal is derived from the frequency of oscillation in the ring oscillator and then used to adjust the amount of heat generated by the heating circuit.
While such an approach can compensate for temperature as well as part-to-part variation, it requires that the CMOS chip run at an elevated temperature. Operation in this condition can lead to reliability problems and also requires greater power consumption.
A similar solution is described in U.S. Pat. Nos. 4,902,986 and 5,345,186. In each of these patents, the ring oscillator is incorporated into a phased locked loop in which the frequency produced by the ring oscillator is compared to a stable reference frequency to produce a feedback signal. The feedback signal controls the supply voltages of the components in the ring oscillator. As the supply voltage is varied, the delay through the loop changes. In this way, the frequency of the signal in the ring oscillator is synchronized to the stable reference frequency. As a result, the delay through the delay chain is constant. The same supply voltage is used to provide pow
Conner George W.
Muething, Jr. Gerald F.
Kreisman Lance
Nguyen Vinh P.
Teradyne, Inc.
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