Low cost bumping and bonding method for stacked die

Details Low cost bumping and bonding method for stacked die Low cost bumping and bonding method for stacked die

2011-01-04

2011-01-04

Luu, Chuong A. (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S107000, C438S109000, C438S127000

Reexamination Certificate

active

07863092

ABSTRACT:
Disclosed is a method of fabricating an integrated circuit assembly in which a plurality of mother dice having a plurality of through-die vias (TDVs) are formed in the first (active) surface of a semiconductor wafer, a substrate is attached to the active surface of the wafer, the second (inactive) surface is back-ground to expose one end of the through-die vias, a plurality of daughter dice are mounted to the inactive surface of the wafer, each daughter die being electrically coupled to a mother die, and the mother dice are then singulated. Attaching the substrate can be accomplished by adhering a glass wafer carrier to the wafer. The wafer carrier allows handling of the wafer during back-grinding the inactive surface, forming under-bump metal (UBM) pads on the TDVs and attaching the daughter dice.

REFERENCES:
patent: 2004/0259288 (2004-12-01), Mostafazadeh et al.
patent: 2007/0164409 (2007-07-01), Holland

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