Low cost ball grid array package

Details Low cost ball grid array package Low cost ball grid array package

1999-07-01

2001-08-28

Gandhi, Jayprakash N. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S767000, C361S768000, C174S250000, C174S260000

Reexamination Certificate

active

06282100

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to ball grid array packages with high density interconnections.
BACKGROUND OF THE INVENTION
Wire bonding has been used in integrated circuit packaging since the inception of IC technology. Wire bonding techniques and wire bonding machines have been refined to the point where wire bonds are relatively inexpensive and are highly reliable. However, wire bonds are rapidly being replaced by more advanced packaging approaches, partly because wire bonds require greater pitch than is available in many state of the art packages.
Among the advanced IC packaging approaches is silicon on silicon technology. Use of silicon interconnection substrates is becoming attractive for high density packages wherein high pin count IC chips are flip chip bonded to a silicon intermediate interconnect substrate, and the silicon intermediate interconnect substrate is in turn ball bonded or flip-chip bonded to a printed wiring board. In many cases these packages use recessed chip arrangements to reduce the package profile.
In these advanced packaging approaches, interconnection pitches can be very small. The earlier technology of wire bonding has been left behind since the high density of I/O's in current IC chips presents a challenge to the capacity of wire bond techniques. However, largely due to the high I/O density of state of the art IC chips, packaging yield using advanced packaging techniques may suffer, and the complexity of the packaging process is increased. As a result the overall cost per bond may be relatively high. The low cost and high reliability of wire bonds makes them attractive if ways can be found to adapt wire bonding to packaging high density I/O chips.
STATEMENT OF THE INVENTION
We have developed an interconnection approach that utilizes wire bonding with high density I/O chips. A typical high density I/O IC chip has an area array of I/O sites that are not easily adapted for wire bonding but can be flip-chip bonded to a silicon intermediate interconnect substrate (IIS) with high reliability and exceptional thermomechanical matching. The silicon IIS is made larger than the silicon IC chip. The high density I/O pattern interconnecting the IC chip and the IIS is fanned out on the silicon IIS to perimeter sites that are then wire bonded to the next board level. This approach marries, in a simple and efficient way, the low cost and high reliability of wire bonds with the high density I/O patterns of state of the art IC chips.
In the preferred embodiment of the invention the fan out layer on the silicon IIS has bare runners, i.e. the conventional polyimide layer is eliminated.


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