Low-cost 3D flip-chip packaging technology for integrated...

Details Low-cost 3D flip-chip packaging technology for integrated... Low-cost 3D flip-chip packaging technology for integrated...

2000-09-13

2002-08-27

Schuberg, Darren (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S720000, C361S768000, C361S718000, C257S707000, C257S712000, C174S050510

Reexamination Certificate

active

06442033

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to packaging of semiconductor integrated circuits for medium-level power applications such as inverters for motor drives and convertors for processing equipment and, more specifically, to modular structures for power semiconductor devices and associated integrated circuits.
2. Description of the Prior Art
Virtually all semiconductor electronic devices from discrete diodes and transistors to integrated circuits of very high integration density require packaging or encapsulation for mechanical protection and support as well as thermal control. In digital logic devices, packaging has been developed quite extensively and is highly sophisticated at the present state of the art; often providing for multi-chip modules containing many interconnected chips or dies. Thermal control has been critical to support high switching speeds of such circuits which may include millions of active devices on a single chip.
However, development of packaging for semiconductor power control devices, referred to as power modules, has not kept pace with the development of packaging for digital circuits and, moreover, requires consideration of a much wider variety of operating conditions and device characteristics than for digital processing and memory circuits having relatively low power requirements and which are not required to deliver significant power levels to an external device. That is, low power digital circuit packaging is principally concerned with reduction of signal propagation time (generally by minimization of signal path length), noise immunity and heat dissipation while there is a trend toward reduction of voltages representing logic states. In sharp contrast, power modules may include one or more large chips of varying sizes which carry high currents and may switch rapidly (although generally at lower frequency than digital logic circuits) or operate in an analog fashion with dramatically different effects on distribution of generated heat and thermal cycling and further including packaging with low-power control and protection circuits. Connections to power chips also must carry large currents.
At the present time, most packaging for power modules is in one of the well-known forms of single in-line packages (SIP), dual in-line packages (DIP), small outline packages (SO/SOP) and quad flat packs (QFP) all of which have been known for a number of years, have high resistance and parasitics, poor thermal management and high cost. Further, because of the requirement for carrying high current, internal package connections (e.g. from package pin or lead frame to chip connection pads) have generally been formed with wire bonds. Wire bonds in power modules are not only subject to high resistance and noise but also parasitic oscillations, fatigue and eventual failure. That is, where the power modules are switching at high di/dt and dv/dt, the connections generate strong electromagnetic fields, resulting in proximity effects and uneven current distribution among bonding wires as well as excess parasitic inductance which can increase the voltages the devices must withstand as large currents are reduced at a rapid rate.
From the point of view of reliability, wire bonding has proven to be one of the weakest areas of power module packaging since high current requires thick 0.25-0.50 mm wires to be employed for wire bonds. One of the main failure mechanisms in high power devices such as insulated gate bipolar transistors (IGBT) modules subject to thermal cycling is wire bond lift-off due to the large coefficient of thermal expansion (CTE) mismatch between metal (e.g. aluminum) wires and silicon chips. Wire bonds may also be effectively damaged by the unavoidable deformation and working of the wire during the bonding process that may generate small dimensional differences that concentrate heat generation and mechanical stress. Motion of the wires to accommodate CTE mismatch during thermal cycling and due to proximity effects cumulatively contribute to fatigue of both the wire and the bond. Therefore, the mean time to failure of power modules is often foreshortened while increased service lifetimes are demanded (e.g. about thirty years) which cannot be achieved with current package technologies, especially including wire bonds.
In recent years, there has also been a demand for smaller power module packages, particularly for portable electronic products where higher power density and better efficiency are desired. Such power modules may increase requirements for control and protection integrated circuits including sensors to be packaged with the power devices. However, power semiconductor suppliers have been concentrating on improving device structure, density and process technology to lower on-resistance of MOSFETS and voltage drop of IGBTs.
Recent advances in these technologies are pushing packaging technology to the limits of performance in these power systems since the resistance and parasitics contribution of the package and wire bonds are now comparable to the values of resistance and inductance of current power chips. In summary, current packaging technology effectively limits performance of current power chips and recent technical developments have not provided overall improvements in performance while available packaging technology does not allow exploitation of the full potential of recent advances in power chips or to support future power chips.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a new power semiconductor device packaging technology which exhibits reduced resistance and inductance and improved thermal performance and reliability at reduced cost.
It is another object of the invention to provide a generalized packaging structure for power modules which will support improved performance of the devices while accommodating inclusion of low power control and protection devices, including condition sensors.
It is a further object of the invention to provide a power semiconductor device packaging which includes chip scale packaging to reduce cost and improve performance.
It is yet another object of the invention to provide an improved solder bump structure and process for improving durability to withstand extreme thermal cycling over long periods of service.
In order to accomplish these and other objects of the invention, an integrated power electronic module is provided including a first multi-layer substrate, a second substrate having a power semiconductor device attached thereto with ball bonds, and an arrangement for assembling the first multi-layer substrate with the second substrate and the power semiconductor device such that the power semiconductor device is sandwiched between the first substrate and the second substrate.
In accordance with another aspect of the invention, a method of making a compliant solder bump structure is provided comprising steps of screening a paste containing a first solder material onto a surface to form an inner solder bump, placing a ball of a second solder material on the inner solder bump to form a middle solder bump, and reflowing the first solder material.


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