Low consumption ROM

Details Low consumption ROM Low consumption ROM

2000-05-24

2001-08-28

Nelms, David (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S104000

Reexamination Certificate

active

06282114

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a ROM, the structure of which enables reducing the dynamic and static power consumption.
BACKGROUND OF THE INVENTION
FIG. 1
schematically shows a conventional ROM structure. It includes a plurality of memory cells
10
arranged in rows and columns. The cells
10
of each row are selected by a respective word line W, and a selected cell presents its data on a bit line BL common to the cells of the same column. An address decoder, not shown, controls word lines W according to the read address presented to the memory.
Each bit line BL is connected to a high supply potential Vdd via a respective P-channel MOS precharge transistor MP. All precharge transistors MP are controlled by a common precharge line P.
Further, bit lines BL are connected to read amplifiers
12
. Generally, the bit lines are grouped in several sets, each set being associated with a single sense amplifier
12
via a multiplexer
14
. Each multiplexer
14
selects the bit line to be connected to the amplifier according to the read address presented to the memory.
As shown, the programmed cells
10
include an N-channel MOS transistor MN connected between the corresponding bit line and the low supply potential, while the unprogrammed cells
10
include no transistor. The transistors MN of the cells of a same row are all controlled by the corresponding word line W.
Generally, read amplifiers
12
are comparators that compare the outputs of the corresponding multiplexers
14
with a reference value Vref sampled on a reference bit line DBL. Reference bit line DBL corresponds to a column in which all cells are programmed. Like a normal bit line, reference bit line DBL is connected to high potential Vdd by a precharge transistor MP controlled in the same way as all other precharge transistors MP.
The elements forming the reference column are chosen so that reference bit line DBL discharges slower, during a reading, than a normal bit line BL. For this purpose, for example, the transistors forming the cells of the reference column are smaller, or less conductive, than the transistors of the cells forming the normal columns.
As illustrated to the left of
FIG. 1
, precharge line P is controlled in phase with the word line W selected by the address decoder. When lines P and W are low, the row is not selected and all bit lines BL and DBL are drawn to potential Vdd by transistors MP.
When lines P and W switch high, the precharge transistors MP are off while the transistors MN of the selected row are turned on and discharge their respective bit lines BL and DBL. Reference bit line DBL discharges slower than a normal bit line. Thus, the level difference between the reference bit line and a normal bit line being discharged increases and reaches a sufficient value to switch a sense amplifier
12
to a high state. The level difference between reference bit line DBL and a bit line BL that has not discharged increases in the opposite direction and reaches a value causing the switching of a sense amplifier to a low state.
A disadvantage of the ROM of
FIG. 1
is that, for each read cycle, the bit lines undergo significant charge variations. Indeed, they are initially charged to Vdd to be discharged to a practically null value. This charge variation results in a high dynamic consumption proportional to the memory read frequency.
Further, in the quiescent state, precharge transistors MP are on. Although transistors MN of the memory cells are off, they exhibit a leakage current causing a static consumption. This leakage current tends to increase with new technologies due to the fact that transistors become smaller and smaller.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a ROM structure enabling significant reduction of the dynamic consumption and of the static consumption.
This object is achieved by a ROM including memory cells connected by columns to respective bit lines and by rows to respective word lines; a reference bit line; sense amplifiers each connected to compare the level of a bit line with the level of the reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line. The duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, are chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.
According to an embodiment of the present invention, the charge transistor associated with the reference bit line is less conductive than the other charge transistors.
According to an embodiment of the present invention, the charge transistors are less conductive than the transistors of the memory cells.
According to an embodiment of the present invention, the memory includes discharge transistors controllable by a common discharge line and respectively connecting the bit lines and the reference bit line to a low supply potential; and means for activating the discharge line after deactivating a word line.
According to an embodiment of the present invention, the read amplifiers include differential stages including differential pairs of P-channel MOS transistors.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


REFERENCES:
patent: 4692902 (1987-09-01), Tanaka et al.
patent: 5680357 (1997-10-01), Sung et al.
patent: 5828601 (1998-10-01), Hollmer et al.

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