Low-consumption charge pump for a nonvolatile memory

Details Low-consumption charge pump for a nonvolatile memory Low-consumption charge pump for a nonvolatile memory

2001-03-28

2003-05-06

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S536000, C327S362000, C327S378000

Reexamination Certificate

active

06559709

ABSTRACT:

TECHNICAL FIELD
The present invention pertains to a low-consumption charge pump for a nonvolatile memory.
BACKGROUND OF THE INVENTION
As is known, the most recent research in the sector of nonvolatile memories, in particular EPROM and FLASH memories, is aimed, on the one hand, at obtaining increasingly higher data storage capacity and, on the other, at obtaining memories that are able to work at a low voltage with increasingly contained consumption during standby.
This research has led to the development of submicrometric technologies which if, on the one hand, enable the production of ever smaller memory cells, thus increasing the capacity of the memory, on the other mean that threshold voltages of the memory cells become increasingly higher, with the result that increasingly higher reading voltages have to be supplied to the memory cells in order to guarantee constantly correct reading of these memory cells.
The reading voltages are currently obtained by means of charge pumps having the purpose of increasing the single supply voltage supplied from outside to the integrated device by such an amount as to enable attainment of the reading voltage necessary for the memory cell to deliver a sufficient reading current.
Generally, charge pumps are affected by far from negligible problems of consumption and of area occupied, especially when the memory devices into which they are built are used in applications that require reduced levels of consumption, such as portable applications (e.g., digital photo cameras, MP3 readers, cell phones, smart cards) or for consumer electronics.
In fact, the aforesaid charge pumps are used not only during the normal step of reading of the memory cells, but must also be able to withstand the boosted reading voltage during standby in order to guarantee that, upon re-entry from standby, an excessive drop in the reading voltage will not give rise to faulty reading or fail to guarantee a memory-read time that is in compliance with the specifications.
In particular, during memory standby, the charge pump supplies a current that is sufficient for compensating the leakage currents that are inevitably present in the integrated device, and this inevitably introduces, during standby, an additional consumption due to the charge pump and to the devices that control the operation of the charge pump.
Numerous solutions have so far been proposed to reduce the consumption of charge pumps.
In order to provide an example,
FIG. 1
shows the schematic circuit diagram of one proposed low-consumption charge pump.
With reference to
FIG. 1
, the charge pump, designated as a whole by number
1
, comprises a voltage-booster circuit
2
having an input
2
a
, on which an input voltage V
IN
is present, and an output
2
b
, on which an output voltage V
OUT
higher than the input voltage V
IN
is present, and being formed by a plurality of booster stages
4
cascaded between the input
2
a
and the output
2
b
, and each formed by a boost capacitor with a high capacitance and by a switch which is closed or opened alternately with the adjacent switch and is made by means of diodes (for example ones made using MOS transistors having gate and drain terminals connected together), or else by means of MOS transistors.
Transfer of charge from one booster stage
4
to the next towards the output
2
b
is upon command of complementary phase signals supplied at input to the booster stages
4
and generated by a phase-generator circuit
6
, which is a logic circuit of a generally known type and essentially consists of a ring oscillator
8
supplying on its own output a clock signal CK having a pre-set frequency and of a non-overlapping-signal generator
10
having an input connected to the output of the ring oscillator
8
and supplying at output a first logic phase signal A and a second logic phase signal B, supplied to the booster stages
4
.
In particular, as shown in detail in
FIG. 2
, the ring oscillator
8
comprises an odd number of inverter stages (three, in the example illustrated), designated by
12
.
1
,
12
.
2
, and
12
.
3
, which are cascaded together, and each of which comprises a PMOS transistor
14
.
1
,
14
.
2
,
14
.
3
and an NMOS transistor
16
.
1
,
16
.
2
,
16
.
3
, having gate terminals connected together and defining an input node
18
.
1
,
18
.
2
,
18
.
3
of the inverter stage, and drain terminals connected together and defining an output node
20
.
1
,
20
.
2
,
20
.
3
of the inverter stage.
Each PMOS transistor
14
.
1
,
14
.
2
,
14
.
3
has moreover a source terminal directly connected to a supply line
20
set at the supply voltage V
DD
, typically 1-3V, whilst each NMOS transistor
16
.
1
,
16
.
2
,
16
.
3
has moreover a source terminal connected to a ground line
22
set at the ground voltage V
GND
, typically 0 V, via a respective limitation NMOS transistor
24
.
1
,
24
.
2
,
24
.
3
having a drain terminal connected to the source terminal of the corresponding NMOS transistor
16
.
1
,
16
.
2
,
16
.
3
, a source terminal connected to the ground line
22
, and a gate terminal connected to a common biasing circuit
26
, which is connected to the supply line
20
and supplies, to the gate terminals, a constant biasing voltage V
REF
generated starting from the supply voltage V
DD
.
In addition, the output node
20
of an inverter stage
12
is connected to the input node
18
of the subsequent inverter stage
12
in the cascade, and the output node
20
of the last inverter stage
12
in the cascade is connected to the input node
18
of the first inverter stage
12
in the cascade.
The ring oscillator
8
further comprises a first capacitor
28
and a second capacitor
30
connected, respectively, between the output node
20
.
1
and the ground line
22
, and between the output node
20
.
2
and the ground line
22
, and have the purpose of determining the oscillation frequency of the ring-oscillator stage
8
.
The operation of the ring oscillator
8
is in itself known and consequently will not be described in detail hereinafter.
Here it is only pointed out that reduction in the consumption of the charge pump
1
is obtained due to the introduction of the limitation transistors
24
.
1
,
24
.
2
,
24
.
3
, that perform the function of limiting the crowbar current that flows between the supply line
20
and the ground line
22
via the PMOS transistors
14
.
1
,
14
.
2
,
14
.
3
and the NMOS transistors
16
.
1
,
16
.
2
,
16
.
3
during switching of the inverter stages
12
.
1
,
12
.
2
,
12
.
3
.
In fact, since the limitation transistors
24
.
1
,
24
.
2
,
24
.
3
have gate terminals biased at a constant biasing voltage V
REF
, they in practice operate as constant-current generators, and since these transistors are arranged in series with the corresponding PMOS transistors
14
.
1
,
14
.
2
,
14
.
3
and NMOS transistors
16
.
1
,
16
.
2
,
16
.
3
between the supply line
20
and the ground line
22
, the crowbar current of each inverter
12
.
1
,
12
.
2
,
12
.
3
can in no way exceed the current imposed by the limitation transistors
24
.
1
,
24
.
2
,
24
.
3
.
The above-mentioned constant-current generators are then controlled by the biasing circuit
26
, which in practice constitutes a control circuit supplying to the gate terminals of the limitation transistors
24
.
1
,
24
.
2
,
24
.
3
a control signal consisting of the biasing voltage V
REF
, as a function of which the crowbar current of the inverters
12
.
1
,
12
.
2
,
12
.
3
can be regulated.
Although extensively used, the charge pumps of the type described above still present certain drawbacks that do not enable adequate exploitation of certain desirable advantages.
In the first place, the biasing circuits
26
that are currently used for biasing the gate terminals of the limitation transistors provided inside the ring-oscillator stages have a multi-stage structure and are of the so-called band-gap type, which use bipolar transistors and resistors, and this type of biasing circuit typically presents, in addition to a considerable circuit complexity, also a no

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