Low compliance tester interface

Details Low compliance tester interface Low compliance tester interface

2000-05-15

2004-05-11

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S757020

Reexamination Certificate

active

06734688

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to automatic test equipment and more particularly a low compliance tester interface for reliably coupling a semiconductor tester to one or more semiconductor devices-under-test.
BACKGROUND OF THE INVENTION
In the automatic test equipment industry, one of the fundamental challenges to testing a plurality of semiconductor devices in parallel involves routing and connecting thousands of ground, signal and power paths (collectively defining tester channels) from the tester channel cards to the device(s)-under-test (DUTs). As shown generally in
FIG. 1
, a semiconductor tester
10
usually includes a mainframe is computer
12
that interacts with a test head
14
. The test head houses the tester channel cards that generate and receive test signals for application to and receipt from the individual DUT contacts formed on a semiconductor wafer
16
. In order to facilitate the eventual connection between each DUT pin and a tester channel, the signal paths from the test head to the DUT are routed through a tester interface
18
. The interface directs the paths from the low-density test head area to the very high dense probe array disposed proximate the DUTs.
Referring now to
FIG. 2
, one conventional tester interface for application to wafer-level testing, generally designated
20
, includes a prober interface board (PIB)
22
comprising a multi-layer circuit board. The PIB includes upper surface contacts (not shown) for coupling to respective channel card coaxial cables (not shown). Lower surface contacts disposed on the PIB underside are arranged in a high-density annular array, and connected to the upper contacts by respective internal electrical paths.
Further referring to
FIG. 2
, the underside PIB contacts correspond to a matching array of connection points on a probecard
24
. Like the PIB, the probecard comprises a multi-layer circuit board that generally routes the signal, ground and power paths from its outer periphery to a centrally disposed probe array
26
. A compliant interconnect array
28
electrically couples the PIB and probecard together. The probe array, during test, touches down onto the semiconductor wafer (not shown) to effect the tester connection to one or more semiconductor devices formed thereon.
Conventional probecards are typically formed in a laminated structure that includes, for example, thirty or more layers, and measures around 0.250 inch thick. Because of the manufacturing complexities associated with such structures, tolerance deviations in the probecard thickness on the order of around +/−0.025 inch are common. Since the surface area of a typical probecard is on the order of approximately 120 square inches, planarity and thickness variations pose a significant challenge to interface designs that require thousands of board-to-board connections over much of the surface area. Moreover, as shown in
FIG. 2
, during operation the probecard tends to deflect near the center portion because of the large number of electrical connections between the wafer and probe array that, taken as a whole, exert a substantial force on the order of around a hundred pounds. Usually, a stiffener
29
is mounted to the probecard in an effort to reduce the deflection. Unfortunately, many areas where electrical contacts touch cannot be backed-up by a stiffener.
The planarity and deflection variations of the PIB and probecard typically have an effect on the assembled tolerance of the vertical, or “Z”-dimension, stack height. Conventionally, the stack height is defined with respect to the bottom of the probecard, thereby including the uncertainty of the probecard thickness in the overall height. Keeping the overall stack height within specified tolerances is very important to ensure acceptable tester performance.
In an effort to compensate for the variations in probecard and PIB thickness and planarities introduced by manufacturing processes and operation induced deflection, and to ensure a constant connection between the PIB and the probecard, ATE manufacturers have typically implemented a tester interface that employs a conventional pogo pin-based interconnect array. As is well known in the art, conventional pogo pins are barrel-shaped contacts having spring-loaded tips that provide a relatively large mechanical compliance up to around 0.125 inch. Having the large compliance allows the assembly of the interface stack to include the PIB and probecard tolerance deviations.
Although pogo pins generally provide a relatively long compliance length, the overall cost and reliability of conventional pogo pins are believed undersirable for the next-generation of semiconductor testers. This belief stems from findings that pogo pin tips are often prone to breakage, possibly substantially affecting a tester's reliability factor in terms of mean-time-between-failure (MTBF). Moreover, the relatively long travel capability, or compliance, for conventional pogo pins undesirably affects the impedance controlled transmission line characteristic for individual signals. As semiconductor device speeds increase beyond 250 MHz, transmission line quality becomes much more important.
What is needed and heretofore unavailable is a low compliance, low cost tester interface having the capability of reliably making tester board-to-board connections. Moreover, the need exists for such an interface that requires little to no modifications to user-controlled hardware. The tester interface of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The tester interface of the present invention provides a low compliance and low-cost alternative to conventional high-compliance pogo pin schemes while dramatically increasing the reliability of connections. This allows for testing of more devices in parallel, contributing to lower test costs per device.
To realize the foregoing advantages, the invention in one form comprises automatic test equipment adapted for testing a plurality of devices-under-test (DUTs). The automatic test equipment includes a mainframe computer and a test head coupled to the mainframe computer. The test head includes a low-profile tester interface having a first interface board and a device board. The device board engages contact points on the DUTs and includes a topside. A hard stop is mounted to the first interface board and defines a reference plane. The hard stop is adapted to engage the device board topside to vertically fix the device board positionally with respect to the first interface board. The automatic test equipment further includes a compliant interconnect array adapted for compression between the first interface board and the device board.
In another form, the invention comprises a method of interfacing a probecard to a prober interface board formed with a bard stop. The method includes the step of first anchoring a top-side stiffener to the probe card. The stiffener is formed with a predetermined reference height and projects vertically in the direction of the prober interface board. The top-side stiffener also includes a defined reference plane for engaging the hard stop. The method further includes the steps of interposing a low-profile interconnect array between the probecard and the prober interface board; and compressing the probecard against the interconnect array until stopped by the hard stop.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


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