Low complexity implementation of a Viterbi decoder with near...

Details Low complexity implementation of a Viterbi decoder with near... Low complexity implementation of a Viterbi decoder with near...

2011-08-30

2011-08-30

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S316000, C375S340000, C375S342000, C375S346000, C375S350000, C714S795000, C714S796000

Reexamination Certificate

active

08009773

ABSTRACT:
A method and system for low-complexity implementation of a Viterbi Decoder with near optimal performance has been disclosed. The Viterbi decoding technique is diagrammatically represented as a trellis. The trellis includes various states at different time instants, and branches connecting these states. Each state has an associated state metric and a survivor path sequence, whereas each branch has a branch metric. The state metric for each current state is checked for crossing a predefined limit. If it crosses the predefined limit, the state metric is updated with a new metric that is obtained by subtracting a constant value from the state metric. Thereafter, the method finds a common path in the trellis at each state and updates the survivor path sequence of each state. The Most Significant Bits (MSBs) of the survivor path sequences of the states at a particular time instant are computed and the original data is decoded, based on the count of ‘0s’ and ‘1s’ in the MSBs.

REFERENCES:
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patent: 7336735 (2008-02-01), Traeber
patent: 7581160 (2009-08-01), Chen et al.
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patent: 2002/0053061 (2002-05-01), Kong et al.
patent: 2007/0168845 (2007-07-01), Endo et al.

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