Low charge-dump transistor switch

Details Low charge-dump transistor switch Low charge-dump transistor switch

2002-09-19

2004-08-24

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

Reexamination Certificate

active

06781434

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to transistor switches and, more particularly, to techniques and structures for reducing transient charge effects therein.
BACKGROUND OF THE INVENTION
Integrated circuits commonly use insulated gate field effect transistors (IGFETs) as switching gates to controllably couple circuit nodes within the circuitry. One type of IGFET that is regularly used in this regard is, for example, the metal-oxide-semiconductor field effect transistor (MOSFET). A control voltage is typically applied to the gate terminal of the IGFET switch to change an impedance between the source and drain terminals thereof in a predetermined manner. When one voltage level is applied to the gate terminal of the IGFET switch, a low impedance condition (e.g., a short circuit) results between the source and drain terminals of the device that will conductively couple circuit nodes attached thereto. When a different voltage level is applied to the gate terminal, a high impedance condition (e.g., an open circuit) results between the source and drain terminals of the device to electrically isolate the circuit nodes coupled to these terminals. Other switching configurations, including those involving multiple transistors, are also commonly used.
As is well known, IGFET devices typically include internal parasitic capacitances that are caused by a physical overlap of the gate of the device with the source and the drain regions thereof. These “overlap” capacitances appear as series capacitors between the gate terminal and the source and drain terminals of the device. The gate-drain overlap capacitance is commonly referred to as the Miller capacitance of the device and will typically appear twice as large as it actually is. When the voltage on the gate terminal of an IGFET switch is varied during circuit operation, the overlap capacitances within the device charge and discharge in a corresponding manner. This charging and discharging of the overlap capacitances will often generate narrow spikes on the source and drain terminals of the IGFET switch due to “charge dumping” from the overlap capacitances. These spikes can cause glitches within the associated circuitry that can negatively impact the operation thereof. Therefore, it is important that charge dumping be kept low in such switches. As the physical size of circuits gets smaller, however, it is anticipated that the relative size of the overlap capacitances within transistor switches will increase.


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Eichenberger, C., et al., “On Charge Injection in Analog MOS Switches and Dummy Switch Compensation Techniques”,IEEE Transactions on Circuits and Systems, 37(2), (Feb. 1990), pp. 256-264.

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