Low capacitance V groove MOS NOR gate and method of manufacture

Details Low capacitance V groove MOS NOR gate and method of manufacture Low capacitance V groove MOS NOR gate and method of manufacture

1975-08-29

1976-08-17

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148175, 148187, 148 15, 357 23, 357 41, 357 55, 29571, H01L 734, H01L 736, H01L 754

Patent

active

039752216

ABSTRACT:
An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.

REFERENCES:
patent: 3355598 (1967-11-01), Tuska
patent: 3412297 (1968-11-01), Amlinger
patent: 3414740 (1968-12-01), Dailey et al.
patent: 3518509 (1970-06-01), Cullis
patent: 3751722 (1973-08-01), Richman
patent: 3752711 (1973-08-01), Kooi
patent: 3761785 (1973-09-01), Pruniauy
patent: 3764396 (1973-10-01), Tarui et al.
patent: 3823352 (1974-07-01), Pruniauy et al.

Affiliated with

Also associated with

Rating

Low capacitance V groove MOS NOR gate and method of manufacture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low capacitance V groove MOS NOR gate and method of manufacture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low capacitance V groove MOS NOR gate and method of manufacture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1484320