Low capacitance power VFET method and device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

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257330, 257331, H01L 2980, H01L 31112, H01L 2976, H01L 2994

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active

059106654

ABSTRACT:
A method and structure for a vertical FET transistor device (VFET) is described for a lower junction capacitance VFET to decrease the switching power loss and achieve increased current capacity and/or deceased thermal dissipation. In a preferred embodiment, the gate capacitance is reduced over prior art methods and structures by etching to the gate 14 and directly contacting the p+ gate with a p-ohmic contact 24. In another embodiment, the area under the gate contact 22 is implanted with a "trim" dopant, where the trim dopant acts to reduce the doping of the drainlayer thereby reducing the capacitance. In another embodiment, the area under the exposed gate contact 22 is isolated by ion damaged to reduce the doping/conductivity of the n- drain layer below a portion of the gate layer to reduce the gate-to-drain capacitance.

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IEEE Electron Device Letters, vol. 16, No. 4, "A Low On-Resistance, High-Current GaAs Power VFET", Apr. 1995, 2 pgs.
"150 Volt Vertical Channel GaAs FET", Campbell et al., International Electron Devices Meeting. Technical Digest, Dec. 1982, IEEE USA, pp. 258-260, (p. 258 col. 2; figure 1).
"High-voltage two dimensional simulations of permeable base transistors", Alley, G.D., IEEE Transactions on Electron Devices, vol. Ed-30, NR. 1, Jan. 1983, USA, pp. 52-60, p. 52, col. 1, paragraph 1, figure 1.

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