Low-capacitance, isotropically etched antifuse and method of man

Details Low-capacitance, isotropically etched antifuse and method of man Low-capacitance, isotropically etched antifuse and method of man

1994-05-25

1996-12-24

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

H01L 2900

Patent

active

055876137

ABSTRACT:
The present invention provides for an integrated circuit antifuse structure having a first metal interconnection line, a programing layer over the first interconnection line, an etch stop layer over the programming layer, a sacrificial buffer layer over the etch stop layer, an insulating layer over the buffer layer, and a second metal interconnection line over the insulating layer. An aperture extends through the insulating layer and the buffer layer. The buffer layer has etching characteristics which are different from those of the insulating layer and the etch stop layer. This permits the aperture through the insulating layer to be formed with substantially vertical sides and through the buffer layer to be formed with substantially sloped sides. The second interconnection line extends into the aperture to form an antifuse structure with a low capacitance and a consistent programming voltage.

REFERENCES:
patent: 5451810 (1995-09-01), Tigelaar et al.

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