Low capacitance interconnect structures in integrated circuits h

Details Low capacitance interconnect structures in integrated circuits h Low capacitance interconnect structures in integrated circuits h

1997-01-17

2000-04-25

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257748, 257759, 257760, H01L 23485

Patent

active

060547693

ABSTRACT:
In accordance with the present invention, an improved method and structure is provided for integrating polymer and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. Since the bond is typically weak between low-k materials such as polymers 18 and traditional dielectrics such as SiO.sub.2 22, the weak bonding may cause delamination or other problems during subsequent processing. The present invention increases yield and simplifies processing subsequent to application of the low-k material by providing an adhesion/protective layer 20 between the low-k material 18 and the intermetal dielectric 22. A preferred embodiment is a spun-on layer 20 of HSQ cured on a hotplate prior to application of the SiO.sub.2 intermetal dielectric.

REFERENCES:
patent: 4843034 (1989-06-01), Hermdpm et al.
patent: 4851362 (1989-07-01), Suzuki
patent: 4879258 (1989-11-01), Fisher
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5073814 (1991-12-01), Cole, Jr. et al.
patent: 5155576 (1992-10-01), Mizushima
patent: 5231043 (1993-07-01), Chan et al.
patent: 5233224 (1993-08-01), Ikeda et al.
patent: 5302233 (1994-04-01), Kim et al.
patent: 5310700 (1994-05-01), Lien et al.
patent: 5336368 (1994-08-01), Iacovangelo et al.
patent: 5352493 (1994-10-01), Dorfman et al.
patent: 5356513 (1994-10-01), Burke et al.
patent: 5366850 (1994-11-01), Chen et al.
patent: 5376591 (1994-12-01), Maeda et al.
patent: 5391921 (1995-02-01), Kudoh et al.
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5413962 (1995-05-01), Lur et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5486493 (1996-01-01), Jeng
patent: 5512775 (1996-04-01), Cho
patent: 5789819 (1998-08-01), Gnade et al.
patent: 5818111 (1998-10-01), Jeng et al.
V.Grewal, et al. "A Novel Multilevel Metallization Technique for Advanced CMOS and Bipolar Integrated Circuits", V-MIC Conf. Jun. 9-10, 1986 pp. 107-113.
Shin-Puu Jeng, et al. "A Planarized Multilevel Interconnect Scheme With Embedded Low-Dielectric-Constant Polymers for Sub-Quarter-Micro Applications", 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 73-74.
Joel r. Wiesner, "Gap Filling of Multilevel Metal Interconnects with 0.25-um Geometries", Oct. 1993, Solid State Technology, pp. 63-64.
IBMTDB, Multilevel Interconnect Structure, vol. 34, No. 9, Feb. 1992, p. 220.
M. A. Hartney, et al. "Oxygen Plasma Etching for Resist Stripping and Multilayer Lithography", J. Vac. Sci. Technol. B. vol. 7, No. 1, Jan./Feb. 1989, pp. 1-11.
Gretchen M. Adema, et al. "Passivation Schemes for Copper/Polymer Thin Film Interconnections Used in Multichip Modules", 1992 IEEE, pp. 776-782.

Affiliated with

Also associated with

Rating

Low capacitance interconnect structures in integrated circuits h does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low capacitance interconnect structures in integrated circuits h, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low capacitance interconnect structures in integrated circuits h will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-995479