Low capacitance interconnect structure for integrated circuits

Details Low capacitance interconnect structure for integrated circuits Low capacitance interconnect structure for integrated circuits

1996-10-10

1998-10-13

Everhart, Caridad

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257760, 257758, 438623, H01L 23532

Patent

active

058216219

ABSTRACT:
An improved method is provided for integrating polymer and other low dielectric constant materials, which may have undesirable physical properties into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. The present invention combines the advantages of SiO.sub.2 with low dielectric constant materials by placing the low dielectric material only between tightly spaced lines. In a preferred embodiment, a low-k material is spun across the surface of the wafer to fill areas between all interconnect lines. The critical areas, or those where the low-k material is to remain are masked off with resist. The low dielectric constant material in non-critical or widely spaced areas is then etched away, leaving the problematic but desirable low-k material in those areas where needed. A layer of dielectric such as SiO.sub.2 can then be applied to fill the remaining areas and provide spacing between metal layers. After planarization, the process steps can be repeated for multiple interconnect layers.

REFERENCES:
patent: 5354713 (1994-10-01), Kim et al.
patent: 5486493 (1996-01-01), Jeng
patent: 5527737 (1996-06-01), Jeng
patent: 5547786 (1996-08-01), Jones et al.
patent: 5591677 (1997-01-01), Jeng
patent: 5635428 (1997-06-01), Martin et al.

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